A new position control register field has been added to the
DSPP PCC on Lahaina. This field controls whether PCC is invoked
before or after GAMUT mapping.
Introduce new PCC control logic to set the PCC position based on
the new PCC_BEFORE flag. Older versions of the PCC control function
now clear all flags to ensure backwards compatibility.
Change-Id: I0a33604111b755e0a0ccf1864a57b17cc9071e3f
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
A new position control register has been added to the DSPP PCC
on Lahaina. This register controls whether PCC is invoked
before or after GAMUT mapping.
Introduce a PCC UAPI flag to indicate if PCC should be placed
before the GAMUT block. By default PCC will be placed after
GAMUT.
Change-Id: I0bcc35e0ce7f87c7fa29922a6a485abe479d893a
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
This change updates plane's dirty flag with QoS
value to ensure QoS gets reprogrammed with new FPS
settings. This is required as QoS values will change
with FPS.
Change-Id: I377b99da2a640d375bd48477f149197b332e7f7b
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Updating qos remap updates requires reading registers to update values,
this adds additional CPU processing when in reality this update
is only needed once.
Bug: 142504774
Change-Id: Iec8d4dfd858b0602db7d2275b6b716dbcffe0d2f
(cherry picked from commit dbd1cfbc21db4b9bd4f1a4fc234cedc314fa1265)
Signed-off-by: Adrian Salido <salidoa@google.com>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Dim layer clearing/setup requires reading registers in order to update
value, doing this add additional CPU processing when it's not really
needed. Add logic to only do the updates only when needed.
Bug: 142504774
Change-Id: I23bcbe39575de35c387cfb7d2b9dc993525e4f98
Signed-off-by: Adrian Salido <salidoa@google.com>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
This change calls setup on blend configuration per stage
instead of per plane per crtc mixer. This avoids unnecessary
register programming if two planes are in the same stage.
Change-Id: I7481270edad13a4182352e72d5d2ab8941de0ae5
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
This change introduces pre-downscaling values to the path where
these values are not provided by userspace. Currently, pre-downscaling
is only allowed by a factor of 2.2 in the x direction. With this
change pre-downscaling will support >2.2 up to 4 in the x direction.
Change-Id: I04d1b07243a5973e9338ea2a212280985b31b6a3
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Add xlogs to capture the secure state information of
each of the planes during mixer setup.
Change-Id: I5d60fb4287b13b3ba5a78c6b858dd244ebeb18aa
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
When there is a race condition between DMS seamless transition and
drm_wait_vblank_ioctl, the latter gets deregistered for vblank
handle as drm_crtc_vblank_on call in crtc enbale increments vblank
count. This change avoids drm_crtc_vblank_on call during seamless
transition when crtc is already enabled as it is not required.
Change-Id: I0b9327a98cef00405b5b94e24a3fd15205339cfc
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
During stability tests there are cases where smmu faults are
seen due to direct transition from secure display to secure
camera without smmu ATTACHED state. Added atomic check to avoid
such transitions.
Change-Id: I307e342f35c6e7dab82902fa77e3a5c0c082f4e4
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
VFP or HFP is adjusted to achieve constant fps during dynamic
DSI clock switch. This feature is not supported for command
mode. So, add check to skip porch calculation for command mode.
Change-Id: I5fa76d6536a55b2a19f24c0e14b6861e1f4c8f25
Signed-off-by: Lipsa Rout <lrout@codeaurora.org>
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
This change updates the parsing of timing nodes to check
the mode of operation as video or command. In command mode,
for each timing node, num of supported dfps rate is always
one. Accordingly, update the num_dfps_rate to 1 for
command mode.
Change-Id: I5098c7e0d4d2320609d6e10031eaef78c1d8b3c1
Signed-off-by: Lipsa Rout <lrout@codeaurora.org>
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Panel's physical width/height larger than 255mm is getting
truncated due to type conversion into smaller type.
Change-Id: I826fb2db542146c07d8379951563430b7da8288c
Signed-off-by: Rajeev Nandan <rajeevny@codeaurora.org>
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Add support to allow creation of debugfs node only if
CONFIG_DEBUG_FS is enabled.
Change-Id: I1ae2c4188a99e3ed88f59fc021efc01407bf942d
Signed-off-by: Harigovindan P <harigovi@codeaurora.org>
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
There are some scenarios where a dfps request
during cwb session will result in cwb
encoder not getting disabled once the cwb
session is over. Add support to fail the
commit if any VRR or dynamic clock change
request is received during CWB transitions
to handle this.
Change-Id: Id3f192f79eac4ad0d7301bd34f7151fec243d685
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
DSI interrupt may be destroyed before it is disabled, it will cause to
the interrupt count can't be cleared, so subtrace DSI interrupt count
in disable function even it was destroyed.
Change-Id: I430b0281957db588c7405d5775d0c10f2f498b36
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Optimize pre mode switch panel command by transferring async. This
removes the time waited until subsequent dma_done irq.
Change-Id: I2e2516fdd641e85d1f1b221a6ea7999c868edf00
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
This change fixes the usecase where dsi msg flags validated only
during command transfer. This fix maintains the flags between
transfer and trigger calls. It also adds a new async override
flag to be used to bypass validate function.
Change-Id: Ie12acd3d7b01099bba65ca37cec61091408b81c5
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Add support to allow creation of debugfs node only if
CONFIG_DEBUG_FS is enabled.
Change-Id: Iaeaf51b3654c9458cf8131a9756e6b905007c4ae
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
The color-processing partial update check wrongly
assumes that all pipes in a CRTC have a DSPP attached.
This inhibits the use of any LMs without a valid DSPP.
Fix the issue by removing this invalid check since whenever
a DSPP feature is required, the HW resource availability is
already confirmed during the color-processing property validation.
Change-Id: I5b4565865644e4a0fa3d0542a299067f21756863
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Restart the timeline for the idle power collapse delayed work
timer for every resource control kickoff instead of only during
a power state change. This will prevent entering mode2 at
unexpected times during active scanouts.
Change-Id: I001157ff7e6b6246e26d537e30d8617cab9cb463
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Add a check to escape the DSC allocation once the requested
number of DSCs has been reached and a pair is not required
for the last DSC allocated. This issue was introduced when
trying to allow for quad DSC, which broke single DSC use.
Change-Id: I4bc368004f92570d588e76ceb832d63fd3bb15d7
Signed-off-by: Thomas Dedinsky <tdedinsk@codeaurora.org>
While running the panel in simulation mode using sim-swte, ESD check is
invalid. The change doesn't set the ESD capabilities if watchdog timer
is being used for TE.
Change-Id: I375f369ad4602f21da6151e526e7b6e78fcea524
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
This change adds support for regdma accelerated programming of
partial update offsets for SPR hw block and validation of ROI
during atomic check based on SPR hw block limitations.
Change-Id: I9e20af4ba7752e8a4af5e9738612c57603163744
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
Current computation of line time does not include compression ratio
from either DSC or VDC. This change stores source bpp and target bpp in
sde_crtc during sde encoder mode set to be used while calculating line
time.
Change-Id: Ib1e045dce17fcf006447d4562b402cc3f214ed8c
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
