The original BA window size given from CP might > max DP supported,
add sanity check based on HAL target allowed.
Change-Id: Ibadaddeffe65165a89d580d8a5cbf5f7c724c809
CRs-Fixed: 3193852
For reo_cmd ring, in current implementation, we call hal_srng_access_end
in case a descriptor is not available before baling out. This may cause
a write to the shadow register for the reo_cmd ring. In case we are in
the middle of WOW, this can be problematic.
Modify existing implementation to use hal_srng_access_end_reap, which
will not schedule a write to the register and simply return.
Change-Id: Ifb83d904e39b3d749522cd246a5ab3fe51a3104e
CRs-Fixed: 3194289
Shadow config v2 can support max of 36 shadow
registers only. For KIWI target, there are 40
shadow registers supported.
Hence add support to send shadow config v3
for KIWI.
Change-Id: If57e6597397da3e239f25a6c0cc24f8fd37dcdf1
CRs-Fixed: 3167758
In ring WRAP around case invalidate the descriptors which
are being reaped
Also use no_dsb invalidate API for invalidate descriptors
Change-Id: Iafa844c81a8364af31520ce5fa3e030073e7c706
CRs-Fixed: 3198373
Currently in some case we are receiving non error packets on REO2TCL
ring, which is causing issue.
Fix is to set DEST_RING_MAPPING_0 to SW1 for REO dest ctrl
register, So that non error packets with reo_destination_indication
with 0x0 in the reo entrance ring will be routed to SW1 ring.
Change-Id: I67f78f35e7dba899943307902d99d0325a60498f
CRs-Fixed: 3150186
Currently window register accessing with PLD lock is not enabled for
HIF path of KIWI, enable it so there is no race condition with HAL
register accessing path.
Change-Id: Iceeba36ca6febdeca0e7f7bc0dcb7d4adc17bc51
CRs-Fixed: 3110425
Prefetch RX HW desc, SW desc and SKB in pipeline
fasion in the first loop of RX processing.
This has improved TPUT by 200Mbps and provided a
10% gain in CPU (single core)
PINE with other optimizations: 3960Mbps @ 100% core-3
PINE + pipeline prefetch: 4130Mbps @ 90% core-3
Change-Id: I47f351601b264eb3a2b50e4154229d55da738724
Added an API to do a batch invalidation of REO descs
saw an improvement of 40 to 45 Mbps.
Note: this change is applicable only for cached
descriptors
PINE with Default driver: 3189 @ 100% core-3
PINE with skb prefetch: 3469 @ 100% core-3
PINE with skb pre + batch inv: 3506 @ 100% core-3
Change-Id: Ic2cf294972acfe5765448a18bed7e903562836c3
This FEATURE_HAL_DELAYED_REG_WRITE_V2 was added to fix the
Audio jank issue, but it could not resolve it completely,
so that was later fixed by existing delayed reg write
support with the help of SMP2P messages to communicate
with FW regarding PCIe link status. This code is not being
used, so removing it and cleaning up the redundant code.
Change-Id: Iada088e72a76b4c071c8a80ee945f36ac959670e
CRs-Fixed: 3056475
Initialize the last_desc_cleared pointer to -1 not 0, and
also fix the check it should always behind tp.
Change-Id: I281e066d45a99ac99d4f3c4e0bcc3f65f14bb589
CRs-Fixed: 2987029
Currently the EAPOL/ARP/DHCP frames arriving as 2K-jump
or out-of-order frmaes are being delivered to the network
stack, without checking for the packet-number sequence.
WCN7850 has hardware support to provide the packet number
of the previous successful re-ordered packet from hardware.
Use this feature to check if the packet-number are in proper
sequence for these EAPOL/ARP/DHCP packets arriving as 2k-jump
or out-of-order packets before submitting it to the network
stack.
Change-Id: I1078452afce4bc00b2509436295e5bd80000feb4
CRs-Fixed: 2965086
WCN7850 has support for near full indication for
the consumer srngs. This interrupt is used to take
preventive actions to avoid ring full watchdog irq
trigger.
Register for the near full irq and add the necessary
ext groups for these near-full irqs.
Change-Id: Ic16381fceabc54e6c52b34dd13abea74cad4d38c
CRs-Fixed: 2965081
Return LMAC start id also as part of hal_get_meminfo API.
This field is added to hal_mem_info struct.
Change-Id: I013d357cf4337702c06a91ed15e8337469865270
While Rx buffers are getting umapped from net rx context if IPA
pipes are enabled at same time from MC thread context this is
leading to race condition and IPA map/unmap is going out of sync.
To fix this introducing IPA mapping lock and IPA mapping need to
be handled with lock held.
Change-Id: I9fa71bdb6d4e4aa93fc795cc5dd472a181325991
CRs-Fixed: 2945063
hal_get_entrysize_from_srng returns the entry size
in dwords but the caller expects in bytes. This results
in insufficient data to be recorded for CE event.
Fix is to left shift the entry size by two bits in
hal_get_entrysize_from_srng so that the entry size
value returned is in bytes.
Change-Id: If532da7abe5ce9c293969f0052455085f18b1926
CRs-Fixed: 2935196
Add iwpriv option 34 to dump the reo rx h/w descs
in DDR for debugging. This cmd will first send cache
flush cmd to REO for all rx tids and invalidate the h/w
cache. Henceforth ensuring that the reo status tlvs and
the DDR values are in sync.
iwpriv wlan0 txrx_stats 34 0
Add fix to ensure bar frame with 2k jump err code is
processed correctly using the REO error code instead of the
REO push reason.
Change-Id: Ia05be668343f3a5d4b3262b8d6a367a50875add5
CRs-Fixed: 2895965
Add wbm head/tail pointer stats to dp_txrx_stats and ring
usage percentage for all SRC and DST rings.
Stats added to the following cmd: iwpriv wlan0 txrx_stats 26 0
CRs-Fixed: 2865996
Change-Id: I7d144d87c5f3485ec9ba85f50b036b69a64e53c6
Enable force wake recipe feature DEVICE_FORCE_WAKE_ENABLE
and disable the generic shadow register write feature
GENERIC_SHADOW_REGISTER_ACCESS_ENABLE.
Force wake recipe will be used to write to the REO remap
control registers by waking up the UMAC instead of using
shadow register writes.
Assert soc wake reg and poll on the scratch reg to check
if UMAC is awake.
Enable HIF_REG_WINDOW_SUPPORT to enable windowed reg
read/write in HIF layer.
Change-Id: Ib696e27e19a07c0084c097b95b7780b56e643c8b
CRs-Fixed: 2850590
Add delayed SRNG register writes support for Tx Ring, also add
dedicated workqueue to do the delayed Tx SRNG register writes.
Change-Id: I8dd157d341f3035e988804eab50d1ca681ab789b
CRs-Fixed: 2868989
WLAN HW can still access the IPA tx doorbell address post
disable pipes if there are any pending tx completions which
could result in a NOC error.
Fix is to reset the WBM2SW ring HP addr to shadow addr in
DDR before pipes are disabled.
Change-Id: I52900eb34530388487923a887354ef8839d8c728
CRs-Fixed: 2846421
Current implementation of hal_srng_access_start() reads the ring pointer
in the same byte-order as it is written by the target. This results in
byte-order mismatch on a big-endian Host because the WLAN target is
little-endian based. For most of the srngs, the target already takes of
this by converting the ring pointer to the host-order before writing to the
DDR. But for other srngs, the Host needs to handle the endianness
conversions. Add HAL APIs to do the same.
CRs-Fixed: 2844519
Change-Id: Ieb47391ac0acc3724e854f433915dd5b1219bebe
Use cache invalidate api instead of cache_sync since
cache_sync api is not available in MIPS platform.
Change-Id: I4b8e2fc3cb9055d1c392c2f6dbe7d6be7c66031b
Excessive logging is detected when force wake request
command fails.
Rate limit the logs in hif_force_wake_request and
hal_write32_mb.
Change-Id: I9b1166074dfdb2d58d811571c802a75a6dbc03c5
CRs-Fixed: 2823961
Add reo ring descrptor swap in case of big endian platform.
Convert msi_data into little endian format before writing into
MSI_DATA register. Also change into little endian format while accessing
the shared LMAC registers.
Change-Id: I07f4ae4e6df4608201b63d325c2cbc37436d1592
REO remap register direct writes as part of SAP stop could
result in a NOC error if the UMAC is in low power state.
Fix is to use shadow register writes for REO remap and
WBM HP registers.
Change-Id: Ie515c3d28f4ccdd99a3757808f1ab6c5cf373e3d
CRs-Fixed: 2813105
Due to recent FW changes not filtering out BAR frames, redirect these
frames to REO exception ring and handle as normal data packets.
Change-Id: I4540929fddab14de57a23f6364fc916a70057cbe
CRs-Fixed: 2795499
Delayed register write work needs to be flushed before bus suspend to
make sure there are on pending writes after driver's bus suspend routine
exits. In case delayed work context is not able to finish before the bus
(PCI) is suspended (DRV), it may lead to a NOC error.
Change-Id: I40cbcec5d23ddd75ec87aed69ac45d95510fa880
CRs-Fixed: 2813733
Add apis to map generic registers to shadow region. Existing
logic includes mapping only srng based regs to the shadow
region.
Add support to map REO control regs and WBM2SW2 rel
ring HP reg address to the shadow region in case the direct
reg writes in IPA enable/disable autonomy fail due to UMAC
block being in a power collapsed state.
Shadow reg mapping for these regs is provided to FW during
init. Add stat shadow_reg_write_fail to track shadow reg
write failure and shadow_reg_write_succ to track successful
shadow writes.
Change-Id: I04790765a3de80047689657e2cad0b73123440b9
CRs-Fixed: 2790321
Adding write/read APIs for accessing the CMEM.
Currently in QCA6750, UMAC and CE windows are statically mapped,
a new static window for CMEM is added for CMEM transactions.
Change-Id: Ie10b33a6f468c6e4db314ea85856414962ef29e3
CRs-Fixed: 2771193
If reo_dst_ctrl register writing failed, this is a fatal error for
IPA pipe going to down case as RX frames will still be routed to
IPA rings then hit NOC error. retry register writing to see any
chance to write successfully, if fail always, trigger SSR or panic.
Change-Id: I3c03faa28e6cc93f396944579a360d5405c8138e
CRs-Fixed: 2774789
The logging macros implicitly takes care of embedding function name
in the log, hence there is no need to include __func__ again.
Getting rid of redundant __func__ reduces driver memory footprint.
Change-Id: I6b5beea990e78486e1e5aab5a8df5fc2f1e5ab51
CRs-Fixed: 2774457
STATUS_BUFFER_DONE tlv written in first word for a status
buffer indicates that DMA is done for that status ring entry.
In existing implementation, for a status ring entry if
STATUS_BUFFER_DONE tlv is not written by HW, we poll on to status ring
entry until DMA is done by HW.
During lmac reset it may happnen that HW will not write STATUS_BUFFER_DONE
tlv in status buffer, in that case we end up polling infinitely leading
to backpressure on monitor status ring.
As per MAC team's suggestion, when HP + 1 entry is peeked and if DMA
is not done and if HP + 2 entry's DMA done is set,
replenish HP + 1 entry and start processing in next interrupt.
If HP + 2 entry's DMA done is not set,
poll onto HP + 1 entry DMA done to be set.
CRs-Fixed: 2740988
Change-Id: Ieef667f0bb4a47e74fc320c93243c637409f47f0
Before accessing any register on chip 6750, check if target is
ready or not.
Do not allow register access if target is not ready.
Change-Id: I41a604d04e861c97bdd676998222ccecbf12fd5a
CRs-Fixed: 2688920
Configure low threshold for monitor ring only when monitor
vap is created. This is needed to avoid spurious low threshold
interrupts on monitor ring since the low threshold condition always
evaluates to true.
Change-Id: I452c0ada84e0a4f18e410c865d8a6a7f50329aef
PCIe window select config reg update goes on different NoC and
actual PCIe device register access goes on the different NoC.
If there is delay in window select reg config, it can result in
access some other PCIe IO memory access and will result in actual
register write lost issue. Make sure to flush the window select
reg write before actual device reg access.
Change-Id: I1fe17aad7ae8fd5dea7a618273d9cd813b236a85
CRs-Fixed: 2687676
In ipq5018 CE registers(0x08400000) kept outside WCSS(0x0C000000) block.
As both regions are more than 60MB apart, not feasible to allocate
single resource which include both.
So, using a separate I/O region to access CE registers.
Change-Id: I67bb6d5ac82a1c0ed1d3e13f7776f9d69ee19956
Currently as part of runtime PM, only the active
tasklets are being drained. For chips eg. QCA6390,
QCA6490 etc, there are grp_tasklets and delayed reg
write work which has to be drained before entering
runtime PM.
Add the logic to drain all the possible tasks
before entering runtime PM.
Change-Id: Ieb486f00fffd7346dcdc1faea6fed5850ef6daf7
CRs-Fixed: 2676000
