There can be a scenario where fps change along with dynamic clock
happen in a same commit. This makes newer dynamic clock configuration
come to impact while leaving panel vblank to function as per the older
configured fps. This is invalid modeset, add validation check for the
same.
Change-Id: I32f15de5260d3abdb16a4b1c3f8eefc8bd634848
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
Change log level for unavailable slave pll from warn to debug
to avoid redundant logs as parrot supports only one DSI.
Change-Id: I200a2f382a1dca7035e4960d3bb0c877867f8ba8
Signed-off-by: Kashish Jain <quic_kashjain@quicinc.com>
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
In the case of DMS the dsi phy timings get updated in
dsi_display_set_mode() and the clock in pre_kickoff().
This brings a mismatch between phy timing and the clock between the
above two operations. For example, during dsi_display_enable(),
the HW is programmed with the new phy timings but the clock is still
running at the older rate. This mismatch can lead to screen flicker
or error.
Update the phy timings and clocks together during pre_kickoff().
Change-Id: I30198e91aba5879b1773103c088d94175639790c
Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com>
Set topology override to cmdline topology before parsing timings so that
correct topology is set in mode.
Change-Id: I7ba371370c71516b436dbe5ec07064f7b54975bb
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
In legacy POMS feature, there were separate timing nodes for
video and command mode. So, while calculating the total number
of modes, 1 extra mode is added for command mode if POMS feature
is enabled in video mode panel.
But as per the new design, this is clubbed into one timing node.
So, there is no separate mode for command mode. This change removes
the check to add 1 extra mode count otherwise it leads to null
pointer dereference while getting lm for this extra mode. Also
avoid overriding mode capability when POMS is enabled.
Change-Id: I73f3b89b22f566e40c88178f2af392214b1ada8d
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
In case of underflow/overflow IRQ storm, send panel dead event from
scheduled underflow and overflow workqueue handler.
Change-Id: Ic6cd6cbae097ea970a392fa99e30b3b620633d40
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
After triggering dynamic refresh, if there is any dsi_ctrl_isr, dynamic
refresh done status also gets cleared as part of it. Because of this,
wait4dynamic_refresh_done timeout error is seen even though dynamic
refresh is done successfully.
Change-Id: I39b42c60d15d9cb0557669f95ff2ed83989f9cd3
Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
Currently we are enabling all the lanes irrespective of the
lanes we are actually going to use. Add support to enable
only those lanes that are required and thus save power.
Change-Id: I9aae76eeaa05a79337d4e4b1f2e36ea9842bd580
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
Since PLL UNLOCK status bit is a sticky bit, ensure this bit
is cleared before unmasking PLL UNLOCK error.
Otherwise unnecessarily DSI controller will trigger error
interrupts for the stale status, the moment error is
unmasked.
Change-Id: I7b7aa63b5e508dde446a4469d9a6625a071dae00
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
Suppose there's a mode change in Nth commit and N+1th commit mode
change request for dynamic clock came even before the Nth commit
mode is set in DSI. Now, restoring the bit clock and porches during
mode set of Nth commit will update the clock and porches according
to the new dynamic clock request which should have actually been
handled in N+1th commit mode set and this can lead to DSI underflow
/overflow.
Avoid restoring bit clock during bridge enable as it is already
taken care during bridge mode fixup.
Change-Id: Ieecb0020a77f5e082a8b9da0ecf461acdbe89e0c
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
To set frequencies for link clks, the clk manager index of
ctrl is require. Use ctrl cell index to get clk manager index.
Change-Id: I175d0721e672fb4d368349584c8b448ba63f4224
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
Acquire mngr clk_mutex before updating link clock frequencies.
Failing this may lead to race around condition while setting the
link clock frequency rates.
Make sure byteclk and pclk rates of PLL are configured according
to clock manager and not the controller.
Change-Id: I2cd26e659ce166d5bc55eb6c060672eeee192bea
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
In the case of DSI underflow or overflow, skip enabling back the DSI error
interrupts and instead send panel_dead. The error interrupt will be enabled
later by HAL as part of handling panel_dead event. Not enabling back the
DSI error interrupts immediately can prevent IRQ storm from occurring.
Change-Id: I769872bb5ac9ef8826c3e4caaab7723901dfc7d8
Signed-off-by: Rohith Iyer <quic_rohiiyer@quicinc.com>
Replace DSI_CTRL_ERROR with pr_err_ratelimited to reduce PHY contention
logging errors, as excessive logging in kernel can lead to system crash.
Change-Id: Ibd81a0e852a73186144ebefc8a1c09020a6e74f0
Signed-off-by: Rohith Iyer <quic_rohiiyer@quicinc.com>
During drm_bridge_mode_fixup, we deny a simultaneous crtc state
change and seamless variable refresh. Incorrect translation logic
between drm_mode and dsi_mode made it such that whenever the dsi
bit clock is not the default value, any drm commit would be marked
with the variable refresh flag, denying all suspends. This change
fixes the suspending issue.
Change-Id: If3c1f603af3e2917f82be6487bee1084a6e1b605
Signed-off-by: Kirill Shpin <quic_kshpin@quicinc.com>
Currently, ctrl lock is taken while waiting for CMD DMA done even in
case of ASYNC command transfer, which doesn't allow any other operation
on the controller until the command transfer is done. Avoid this by not
taking ctrl lock while waiting for CMD DMA done.
Change-Id: I91f2638fa02f48ec4c7a41c750daa46b52c5e2f2
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
During qsync frequency step down, it is possible for the changing
frame window to lead to frame buffers being transferred when it
is unsafe to update. Pineapple r2 hardware supports using the
panel's TE level, instead of the start window, to trigger the
frame transfer.
This change enables using TE level during QSYNC or AVR, if the
hardware supports it.
Change-Id: Ie675edaaeb80921c639905395b709f4c67134fc7
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Add dsiclk_sel support for both DPHY and CPHY, update pclk_div
calculation w.r.t dsiclk_sel as per HPG.
Change-Id: I573addd62c77d1c9f089b7aadf386cd2e579f442
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
Signed-off-by: Kirill Shpin <quic_kshpin@quicinc.com>
Rename dsi_clk mux as dsiclk_sel to match the naming convention
with HPG.
Change-Id: I50671a78fccdd10d74d43fdf8ef4ede0c55fd09b
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
Signed-off-by: Kirill Shpin <quic_kshpin@quicinc.com>
Support 8bit and 10bit bpp switch for display.
Change-Id: Ia5fcb330df95618596377773d0598be2b5609de1
Signed-off-by: Yahui Wang <quic_yahuiw@quicinc.com>
In case of DATABUS_WIDEN, follow the HPG to calculate bitclk,
byteclk and pclk. Configure the DST_FORMAT and the clock
dividers in DSI PHY and DISP_CC w.r.t. the bpp before
compression.
Change-Id: I526eab5bc88b8d667b8b1a0d257b2f147998286a
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
Signed-off-by: Kirill Shpin <quic_kshpin@quicinc.com>
Change increases cmd dma timeout to 1200 milliseconds from 200 milliseconds.
There are video mode panels which can support one frame per second, if pixel
data transfer is active, then our command transfer timeout should be atleast
1000 msec.
Change-Id: I3d650d787fa6557ce474aca977906b99af1f1cbc
Signed-off-by: Rohith Iyer <quic_rohiiyer@quicinc.com>
Sets DSI priority level to 7 before any commands are triggered.
This DSI priority setting is recommended by systems team as DSI
and Lutdma uses same Xin for fetch.
Change-Id: Ife6dee5ed51874818168d92728f76108495b8727
Signed-off-by: Rohith Iyer <quic_rohiiyer@quicinc.com>
Currently we are always doing command transfer cleanup which includes
disabling command engine, clocks, gdsc and unmasking overflow interrupt
as part of post command transfer function only after CMD DMA wait is
done. Cleanup should also be done if an ESD failure happens before
kickoff of a batch command. Organize code so that command transfer
cleanup can be done irrespective of whether command kickoff is done
or not.
Change-Id: Ieb92daa7f5da62c16c71f1b23ceff20adfbf3621
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
Reset number of bytes read from panel to the expected value when panel
sends more bytes than requested during DSI read. This can otherwise lead
to negative value of repeated bytes and array out of bounds access.
Change-Id: I9310c521a862108940142ba7c1a8c39838be0f79
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
Qsync ON/OFF commands have to be sent to the panel before connector
kickoff and sending them in the commit thread blocks it for few
millliseconds, and can lead to frame drops. Avoid this by sending
them asyncronously.
Change-Id: Ia7bc694871faf02b7c1a068b3d0ee7056c272506
Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
Replaced lane swap register for lane swap in DSI controller.
Added check for where to perform lane swap based on DSI controller
version. Replaced function to parse device tree data for lane swap,
as previous function did not work.
Change-Id: I5e50a761b6ac0d2658ba73a5648e2f80f3470b96
Signed-off-by: Rohith Iyer <quic_rohiiyer@quicinc.com>
In dual display configuration, where only one display is active at a time,
dsi0 and dsi1 can be used to drive primary large display and, one of the
dsi (dsi0 or dsi1) can be used to drive secondary display. This helps to
time division multiplex shared DSI for primary and secondary panel which
solves the bandwidth limitation problem. This change adds support to allow
sharing of dsi ctrl and phy between dual displays.
Change-Id: Ib4ed1bf51f587b544ec24b1b558ff83225b36e4b
Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
The clk_ctrl_cb and post_cmd_tx_workq callbacks are assigned
to individual ctrl during display bind. In case of dual display
with shared DSI, where primary display has ctrl0 & ctrl1 and
secondary display has ctrl1, the callbacks of ctrl1 of the
primary display gets overwritten with the callbacks of ctrl1
of the secondary display.
In the shared DSI design, only one display will be active at
a time. So, move the callback assignment of clk_ctrl_cb and
post_cmd_tx_workq to display prepare to fix this.
Change-Id: Ic02fa2f00c430fd5759400e06d82d004d4f7cba4
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
