Current mode fixup validates mode against both state mode and crtc mode
which causes mismatch between validation and drm_mode_equal check.
Perform validation against the same mode (crtc->state->mode) to avoid
mismatch and reflect proper state.
Change-Id: If5647f2df0275cc14dd8d761d16e58fd0aa775f7
Signed-off-by: Adrian Salido <salidoa@google.com>
Signed-off-by: Lakshmi Narayana Kalavala <lkalaval@codeaurora.org>
Create a data structure to maintain available hardware resources
and track capabilities. This data structure is used to send
the current available resources and caps information to
connector ops get_mode_info, get_modes and validate_mode to
process the display mode.
Change-Id: If38fc628ee5ab4729821f88c0050ab45375187b8
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
Change updates frame transfer time calculations. Frame threshold
is provided as input to decide on the final transfer time.
Panel dsi clock node followed by mdp transfer time node
will take priority in selecting final transfer time than frame
threshold time.
Change-Id: I40c3abfc635cd9b338b705535612ac32e047ce6e
Signed-off-by: Vara Reddy <varar@codeaurora.org>
allow other device drivers to find this drm panel in global registry
Change-Id: I945bdbe9d8ed85dbb20f876e72687d6363c27492
(cherry picked from commit 9fd9ee68951d477aa9be580b047adcb72eff55c3)
Signed-off-by: Harpreet "Eli" Sangha <eliptus@google.com>
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
This change updates the DSI_MODE_MAX macro from
5 to 32.
Change-Id: Ic5ef1005bec525248315daab71bae9ac591ee149
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
The change adds a check to make sure the length of bytes being
copied don't exceed the size of the destination buffer
causing an overflow.
Change-Id: Ib3ca3705e4179ccda1af11279e96e167baee6a3b
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
For DSI PHY timing of version 4, adds the missing configuation
of phy_clk_params and updates some extra clock parameters.
The less precision during calculation is fixed, which is caused by
not exactly following PHY timing document.
Change-Id: Ibb75d4d3e5b4a5979ff4a85dba1accf3677a6584
Signed-off-by: Yujun Zhang <yujunzhang@codeaurora.org>
This change updates the DSI PHY sequence for Kona target as
per latest HW team recommendation.
Change-Id: I110cc5044d2676ade58f947b3efca53d1d72753c
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Continuous splash enabled displays are identified by reading
the MDP ctl registers. DSI cont-splash init settings are
called based on this. Additionally, DSI reads the DSI-CTL
scratch register set by bootloader to detect cont-splash.
This change removes the redundant mechanism in DSI to
detect cont-splash.
Change-Id: Ic58be1e62eda239fcea5e82d9d356905dc552a73
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
This change adds support for dynamic switching of dsi clocks
to avoid RF interference issues. DSI PHY V4 support is added.
Change-Id: I5bdbd6d2916692087c0192d23c8e7598238f161f
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
Signed-off-by: Yujun Zhang <yujunzhang@codeaurora.org>
Currently the dynamic bit clock switch trigger for command mode
is supported via sysfs node. This might lead to unnecessary
race conditions, when dsi driver is enabling the dsi bit clock
as part of commit and at the same time if bit rate change via
sysfs happens. So make the trigger happens via kernel mode set
call as done for video mode.
Change-Id: I17acb408d2b6dbd6fa41994e56262e31e43d088b
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
Signed-off-by: Yujun Zhang <yujunzhang@codeaurora.org>
This change adds support for dynamic switching of dsi clocks
to avoid RF interference issues. Also with dynamic dsi clock
switch feature coming into picture, now populate the supported
refresh rate as list instead of providing a range. Modify the
logic to enumerate all the modes in dsi driver, taking dynamic
bit clocks, resolutions and refresh rates into account.
Change-Id: I5b6e62bc935cf2234bdd96fcb3c7537b4e735fff
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
Signed-off-by: Yujun Zhang <yujunzhang@codeaurora.org>
This change ports the missing changes from 4.14 to 4.19
that were missed. It includes changes up until
commit 0f8fb25421ff ("cnss2: Add device version to
SOC info structure").
Change-Id: Idfdfe891f146e389e3c65cc3fc4c98d93220e789
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Currently dynamic mode-switch is allowed only after
the cont-splash handoff is handled during the first
frame. Remove this restriction for cmd-mode alone as
it can handle the use-case.
Change-Id: I5f9dc758f50a91fec0b9f710c74f2ea78c4e75eb
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Primary and secondary displays should have first priority
when reserving lms. Static reservation can potentially block
higher resolutions for the required displays. This patch gets
the layer mixer requirement for primary or secondary display
if available. It reserves those layer mixers dynamically
for the respective display when connector is registered.
Change-Id: Id69dac4c72d6b20008049f4aeb71c0f97d0a426b
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
For some phy ver 4 chipsets, DSI_PHY_CMN_CTRL_4 needs to be programmed
in normal power up sequence. This change adds support to program the
same based on minor phy version.
Change-Id: I68bed48ca671f540efafd13f8d56c7e90de8b25c
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
Add support to selectively enable clock gating for supported
DSI clocks using a new debugfs node - config_clk_gating. This
new node would be created for every display node. See below
for usage examples:
To enable clock gating only for BYTE clock:
echo 1 > /sys/kernel/debug/<display_name>/config_clock_gating
To enable clock gating only for PIXEL clock:
echo 2 > /sys/kernel/debug/<display_name>/config_clock_gating
To enable clock gating only for PHY clock:
echo 4 > /sys/kernel/debug/<display_name>/config_clock_gating
To enable clock gating only for all clock:
echo 7 > /sys/kernel/debug/<display_name>/config_clock_gating
To disable clock gating for all clocks:
echo 8 > /sys/kernel/debug/<display_name>/config_clock_gating
To go back to default setting:
echo 0 > /sys/kernel/debug/<display_name>/config_clock_gating
Change-Id: I83713d86eb1b9675d40d51fc20de81cca0aeb1c0
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
If we set esd check mode as TE signal check for video mode panels
the panel will be continuously reset. This change doesn't allow
TE signal check as ESD check mode.
Change-Id: I42a09d605b259d9f06c67cb126d3684ed4489699
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
This change fixes the invalid memory access. It allocates
enough memory so that out of bounds access is avoided.
Change-Id: I0749eac54cfa91891a4377b99fbd7f24dd3bd02a
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
This change updates the checks needed before setting the flag
to enable panel switching between command and video mode.
New crtc active state remains disabled and it causes a failure
in the previous case.
Change-Id: I059731d2faa0f7844d3784fcf7694509fbba3ff7
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Change updates dsi clock calculations for command mode
as per recommendation. Now dsi clocks are tied to
frame transer time. Propagate correct frame transfer
time to hal to update mdp clocks and bandwidth needed
accordingly.
Change-Id: I46f9038622ddd47cc53c5f3d54229f69a7008c8a
Signed-off-by: Vara Reddy <varar@codeaurora.org>
Remove the redundant register dump sub range
registration for DSI ctl/phy as it needs only
the base registration, since it is considered
as a single block.
Change-Id: I11546bfcde05d02849c53577c4546dcfa9203539
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
DSI display may support video mode and command mode both and it may
support transition between these two modes.
This change adds seamless transition between these two modes for DSI
display by avoiding crtc enable/disable and panel power on/off
during modeset.
Change-Id: Id7ddaef7d1f0f7cc7d52283755bad53a246adec6
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
Fix few DSC parameters related to 10 bits-per-component
10 bits-per-pixel configuration according to HW programming
guide.
Change-Id: I3ceb1eb9b1247440ef68800e9b62e9ffb7ec5b57
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Add runtime_pm ops support in drm driver instead
of direct sde_power_resource_enable/disable call.
It allows drm driver to use runtime pm refcount logic
to track the resources instead of custom implementation.
The change also removes the NRT_CLIENT support from
sde_power_handle code to simplify it further.
Change-Id: Ib14692dca5876703d0a230da2512d731b69b8ebb
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
This change brings msm display driver including sde,
dp, dsi, rotator, dsi pll and dp pll from base 4.19 kernel
project. It is first source code snapshot from base kernel project.
Change-Id: Iec864c064ce5ea04e170f24414c728684002f284
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
