During suspend commit, crtc_commit thread is blocked waiting
for touch response in drm_panel_notifier_call_chain and
rsvp_nxt pointer clear in drm_atomic_state_put is pending
(>100ms wait) which was allocated in atomic_check. When
resume commit is triggered early, RM poll timeouts are seen
due to rsvp_nxt pointer is not cleared and thus causing
power on commit failures. This change avoids RM reserve
during atomic_check of suspend commit as msm_crtc_set_mode
returns early and rsvp_nxt is not used elsewhere in commit path.
Change-Id: I6d76ec7cc07f6961b909febd3d9d932b46052c17
Signed-off-by: Akhil Jaiswal <quic_akhijais@quicinc.com>
Add changes to skip RM allocation during atomic_check for dsi connectors
which can have a seamless transition during CWB usecase. When CWB gets
enabled in alternate commits N, N+2 on dsi connectors there is back to
back connectors_changed modeset and poll gets enabled for the
consecutive commit N+1, N+3 on rsvp_nxt to get cleared. This rsvp_nxt
will be cleared on drm_atomic_state_put of commit N, N+2, hence
atomic_check of commit N+1,N+3 is blocked until this time causing commit
failures.
Change-Id: I320969862b8838a70a8cd3909d244c23871eb430
Signed-off-by: Charishma Jerripothula <quic_cjerripo@quicinc.com>
This change fixes the double freeing of physical
encoder ptr which contains the same memory address
in case of video or command mode usecase.
Change-Id: Ic5704201785494d36142ec3065575f527e96475c
Signed-off-by: Gaurav LNU <quic_glnu@quicinc.com>
This change removes tx_wait during DMS for targets which have
dsc_hw_rev_2. For targets with dsc_hw_rev_1, during DMS the
tx_wait is needed since DSC registers are not double buffered
and frame trigger needs to be serialized to avoid pp_timeout
issues.
Change-Id: Icf3c0e0ed0cf9369db634419cfb28fcccbe88b8b
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
In POMS use case while disabling the virtual encoder, the virt
reset function sets the current master to null. concurrently, if
there is a query from the DRM client for the current vsync count,
it returns a zero value. This results in the blocking of the
drm_crtc_funcs.disable_vblank function. since the vsync count
has been relocated to the virtual encoder, remove the physical
encoder structure.
Change-Id: Ie692df657b5a86b6b8915a15e9a070642243fcfb
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
In POMS use case, the handling of the wait for vsync event
completion coincides with the concurrent
drm_crtc_funcs.enable_vblank. This concurrency causes a vsync
event complete timeout while disabling the encoder. to fix this
concurrency problem, increment the vblank refcount in encoder
disable and release the vblank refcount in encoder enable.
Change-Id: I79671e4a2bafdd01a6b2523a80fe511bff23d6b6
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
In CWB use case along with suspend commit, the function
drm_crtc_funcs.get_vblank_counter returns a zero vsync count
value. This causes blocking of drm_crtc_funcs.disable_vblank,
leading to a wait for vsync timeout while disabling the encoder.
hence clear a cwb encoder mask in encoder disable and set it
while performing mode set.
Change-Id: Ic994aa0a86faf48e2b25955cf6fe12166fe9d328
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
Introduce vsync count variable in virtual encoder structure
to keep the vsync count variable value in sync while performing
the poms. Consequently, this prevents the blocking of
drm_vblank_put and the invocation of
drm_crtc_funcs.disable_vblank.
Change-Id: I74903a89b17a8f46fb1b21338500553f36771dd0
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
In lower fps the scheduled off_work for idle pc race with
crtc_commit thread causing janks in display. This change
updates the time required to enter idle_pc based on frame
rate instead of default time. It also sets max and min bound
for optimized performance.
Change-Id: I514015361d6773156971dcc5801ed4b75d78db86
Signed-off-by: Yojana Juadi <quic_yjuadi@quicinc.com>
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
During PM suspend in dual display usecase, the power off commit to
turn off primary and secondary crtcs is done with only one
drm_atomic_state scheduled on primary crtc_commit thread. At the
same, touch events can happen on secondary panel, which will
run input_event_work and schedule the sde_enc->delayed_off_work
to turn off its enabled resources. There can be race between primary
crtc_commit thread which unregisters input_event, cancels
all the pending works before setting sde_enc->cur_master to NULL
and input_event_work_handler which schedules the delayed_off_work
without checking the input_event_handler state.
This change adds input handler unregister check before triggering
_sde_encoder_rc_early_wakeup.
Change-Id: If6de3d45ccda5d0b84065a1a76964c1ab00eeaa1
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
While transition from very low fps (1Hz) to higher fps (120Hz)
there will be a delay on first frame to take effect on
mode switch. In such cases if kickoff_timeout value is programmed
based on newer high fps wr_ptr_timeout can happen. To avoid this
update the kickoff timeout with respect to lower fps and reset
it back according to present fps once the mode switch commit is
done.
Change-Id: I08e1a68bb1e388a1bda8ef61d47e9eb4b2fc97fe
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
If cont splash is enabled, wait for autorefresh_status to be idle for
1 vsync in prepare kickoff. This patch also prevents entering to
rsc_solver_mode if autorefresh_status is busy.
Change-Id: Id7491361dae2482905e10a5a10e590d5f5b49e6f
Signed-off-by: Yojana Juadi <quic_yjuadi@quicinc.com>
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
When wfd display is connected, qseed3 coefficient lut programming
is getting erased due to idle pc entry for wfd pipes. On idlepc
exit commit, plane properties are not reconfigured from userspace
since support is not present for writeback crtc. This patch
updates idle pc handling to avoid gdsc power off when writeback
crtc is connected and for CWB encoder gdsc power off will happen
on idle pc entry.
Change-Id: I7f75bf45089acaf1bd1b775351e05bcdcc89fc9e
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
The current scenario is as follows commit N with autorefresh
enabled and frame starts processing. On suspend commit N+1,
during virt_disable software resets CTL path after autorefresh
config is disabled. Since in hardware frame is still processing
sw reset is causing fifo underflow. This change waits for
vsync so that current autorefresh frame transaction completes
before issuing a CTL_SW_RESET.
Change-Id: Ib0662837e54b14cea6ab835a1093a2f048c473be
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
In some corner cases there is pending vsync timestamp event to
sf when encoder is getting disabled. This is keeping vblank irq
to be enabled after sde_encoder_virt_reset leading to NULL ptr
access. In these cases, wait for vsync event to be completed which
disables the irq.
Change-Id: If0a6be1fc282906fb1b9c0fd18ede1d31d2549b3
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
RSC Solver enable during autorefresh enable need to be avoided.
Currently in SDE driver, solver is disabled if autorefresh is
enabled from HLOS client but autorefresh disable transition is not
considered. This change avoids RSC solver mode in autorefresh
disable transition commit including splash hand-off.
Change-Id: Ib1c4791b203892629abdd84999671830a61f6ed0
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Passing the same error code received from the input fence error.
Change-Id: I59865e89eb974d1ee9f7c2fe3e13acd66cb82617
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
This change avoids wait for EPT to timeout in non-qsync panels
when the EPT time is within last & next expected vsync time
calculated based on current fps for panel.
Change-Id: I9e385c14a20994b29b5bc4afb024f147e6cc035c
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
Support 8bit and 10bit bpp switch for display.
Change-Id: Ia5fcb330df95618596377773d0598be2b5609de1
Signed-off-by: Yahui Wang <quic_yahuiw@quicinc.com>
Remove the validation check that rejects the concurrency of
Expected Present Time update during modeswitch, as it is
expected to get an updated EPT value during the switch.
Change-Id: Ia94aedc4ea39b9c72fb0db17e91a09a77086563b
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Move Expected Preset Time delay from prepare_for_kickoff phase to
just before encoder kickoff. This will ensure the delay is done
towards the end of frame trigger and keeps minimal s/w programming
after the delay. This will help in cases where other unexpected
system delays occur, while coming out of sleep.
Change-Id: Ia04a9ab0455db8082b3f9f03d02db2cec5e17db5
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Add a new clear_flush_mask ops in sde_hw_ctl_ops.
Flush mask update to cancel the fence error frame with
the new ops.
Change-Id: I8d03d8e83a05a652789fb38e885a3c8497e4d262
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Fence error handling for wb and cwb retire fence.
Signal the retire fence for the fence error frame.
Change-Id: I0f73195c50edab4b8aefb58cea342214be87584c
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Add framework for display submodules like PP, DSI, DP to register
for fence error and call the client callback funtion when fence
error occurs.
Change-Id: I70cc6b01907177e6c4238c4398fe2c085a000322
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Sw fence error handling addresses following:
a. out of order handling
- For cmd panel, signal the release fence and retire fence once
sw fence error detected.
- For vid panel, signal the fence error frame release fence and
retire fence once sw fence error detected, hold the release
fence of last good frame till next good frame.
b. avoid BW decrease vote
c. lut dma reset
d. cancel kickoff
Change-Id: Ic496c532a26d80e0ef0074624ef6ace01c4ab2f0
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Handle out of order dma fence signalling and propagation of fence
error. Out of order fence signaling is required only in Video mode.
For example, in case of N, N+1, N+2 frames where N, N+2 are good
frames and N+1 is frame with fence error. The release fence signal
sequence in video mode would be N+1, N, N+2.
Change-Id: I8b6f88cfeee945e28571b765f24ffea22fad23b8
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Register callback function to hw fence driver and implement the
callback funtion.
As part of fence error handling, address out of ordering of HW
fences, SW override for release fence signal and handle BW voting
in both cmd and video mode.
Change-Id: I22902762b4cc09a5f5a20cf0dd01fc336a0f0cb4
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
In non-qsync panels when min FPS is not published in DT,
the default min fps is set to 10 FPS. This change handles mode
switch cases, when panel FPS drops below 10 FPS by updating
min FPS to panel FPS for Expected Present Time calculations.
As part of the change, reduce 2ms from EPT to account for
scheduling delays after schedule_timeout.
Change-Id: Idc206f39adfb3517b4ea2cfa303fe53182a8e63e
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
With DP plug-ins, it is possible for the connector fill modes API
to be called to update available modes on the connector and at the
same time have the commit thread calculate the max mode width
on the available modes. As a result, it is possible to access
pruned modes from the modelist.
This change moves the calculation into the fill modes call-flow,
so that the max mode width is determined once, and stored to be
used during virt enable.
Change-Id: I6c332c57e6e98ed98444a303add97d163a2031bf
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
This change adds hardware programming that will update the
txq wr_ptr upon output fence firing.
Change-Id: I79ff0ea5fb2b7f73a48bd70e3c8e71ea69fead95
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
PPB size programming checks for the max horizontal width of the
panel by checking all available modes. In some DP usecases,
it is possible that this information is not ready at this point.
However, this is not an error, as by default driver will set the
maximum size.
This change reduces the error log to a debug warning.
Change-Id: Ieb63524457db410a2569682f2c3863e082c60805
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
MDSS 10.0 onwards, hw supports programming of pingpong
latency buffer size based on the resolution of display.
In prior targets full size of the latency buffer is used.
This change adds required support in sde driver to program
the pingpong buffer size based on systems recommended
latency lines requirement and the display resolution.
Change-Id: I172b19e5b397eb86190de57fed36f24cd67d2207
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
Introduce a new connector property called “EPT_FPS” for the cmd
mode panels. User space will set the “EPT_FPS” based on the
intended content fps, relative to the last retire fence timestamp
as calculated by Surface flinger. Program start window based
on the Expected Present Time fps.
Change-Id: I24b93e0f941af9fb2422b2484328254d04a1acbe
Signed-off-by: Shirisha Kollapuram <quic_kshirish@quicinc.com>
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Add capability to read avr step for each timing mode. This will
be in addition to the existing avr-step-list which is defined
when dfps is enabled. Expose the avr-step as part of each
mode in connector caps to user-mode.
Additionally, change the avr_step connector property to enum
to give usermode just the capability to enable/disable avr-step
and not alter the step value as its fixed from the device tree.
Change-Id: I6d7f8e9fcf03f98abef7640fc741e5e1be8597a1
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Time the flush bit setting to match with the expected frame
rate. To achieve this, introduce a new connector property called
“Expected_Present_Time”. User space will set it based on the
intended content fps and AVR step, relative to the last retire
fence timestamp as calculated by user space. Delay the frame
trigger to match with the EPT.
Change-Id: I0b86caaa53ee2e37671167acdffd22ec62b4e9ae
Signed-off-by: Shirisha Kollapuram <quic_kshirish@quicinc.com>
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Starting with HW-Fencing, the frames hw kickoff
can take longer to trigger, given that HW will wait for the
input fences signal. Therefore, this change increments
the time-outs to wait up to ~10 secs, which corresponds
to the current input dma-fences timeout. This ~10secs
wait is given in intervals, where the dma-fence is also
checked, so in case that the client producer of the fence
signals the dma-fence, but misses the hw-fence signaling,
Display driver can handle this case and do a sw-override
to start the fetching of the incoming frame without waiting
for the input hw-fence ipc signal.
Change-Id: I6fcacbbaa79ca9847da616bd52efdda4bb8fccae
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
Timing DB needs to be disabled after panel vnsyc.
Update the wait time to reflect difference in line time
between MDP and panel vsync.
Change-Id: Ib5282d67995e8379ead928218f31a8f9fe7fa978
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
This change adds support for dynamically enabling and disabling
additional physical encoder IRQs.
Change-Id: I500fa69d1b8b8df39fd608391c906257efdea63b
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
As per DP HPG recommendation, controller flush mode is
set to be synchronous with a vsync. This requires a
peripheral flush to be issued for HDR SDP to be processed.
Currently in a static HDR use case, since the peripheral
flush is not issued after queueing an HDR SDP, it never
gets sent to the sink and it stays in SDR mode. This change
issues a peripheral flush on every DP commit, so that
any pending SDPs are flushed.
Change-Id: I0ed82b6cd8df33539a3067c6ad9827f74de2ed51
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
