Commit Graph

45 次程式碼提交

作者 SHA1 備註 提交日期
Christopher Braga
87e6558847 disp: msm: sde: cleanup naming in sde_color_processing
As the number of cp features has continued to grow, the file
sde_color_processing has become increasingly harder to parse.
Update function and parameter names to better identify internal
functions and increase readability.

Change-Id: Ib82d6c9a45b36b932ab3a2d573b7cbe13a6c10bc
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
2021-03-17 11:22:07 -07:00
Gopikrishnaiah Anandan
320ae88cf1 disp: msm: sde: avoid caching color processing properties in validate
Recent investigation shows that color processing properties are
incorrectly being cached in validate. This can result in unwanted
color processing properties being applied if a previous commit
failed or was validate only.

Add color processing properties to sde crtc state instead of marking
them dirty in color processing driver. When atomic commit is called
properties from state will be marked as dirty and applied.

Change-Id: If231a1f028e4cbd0b50eb0a947f4d58f94390a0c
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
2021-03-17 11:22:07 -07:00
Nilaan Gunabalachandran
8e2e3358d6 Revert "disp: msm: sde: Avoid kcallocs in atomic commit path"
This reverts commit 6886d03e4a.
It tries to memset the pstate from UI thread (crtc atomic check)
and crtc commit thread.

Change-Id: Ic9d3e5555d7085832df76025e53488d2b3365739
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2021-03-02 09:06:22 -05:00
Gopikrishnaiah Anandan
e7c7283510 disp: msm: sde: add support for noise layer
DPU has added support for noise injection into the layer stack. Change
adds support for noise layer programming and exposes the hardware block
to the user space modules.

Change-Id: Id176eea54fcdcd5d399457b14133a1ccde07299f
2021-02-23 15:56:36 -08:00
Chandan Uddaraju
4fe3d97078 sde: wb: add changes to support Dedicated-CWB
Add new capture/tap point as CRTC property for
D-CWB feature. Update the hardware blocks and
corresponding APIs to configure D-CWB data path.
Add new hardware pingpong blocks that
are dedicated for CWB.

Change-Id: I22576df1768b50f9f47d8527f62913b01ff4d9a7
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
2021-02-19 12:52:59 -08:00
Samantha Tran
6886d03e4a disp: msm: sde: Avoid kcallocs in atomic commit path
To avoid kcalloc for the multirect plane states and plane states will now
be stored sde crtc. These states are populated momentarily and accessed in
a single context for a handful of functions then are not used. This will
clean up parameters passed between functions in the commit path as well.

Change-Id: I6a8116a43c140b3f1c0464734032b8db13c1cfb0
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2021-01-28 08:04:08 -08:00
orion brody
d00d481360 disp: msm: move from drm_mode to msm_mode
Move away from the private and private_flags fields from drm_mode,
as it is being deprecated in latest kernel version. Instead, Add
msm_display_mode as a wrapper to be used in downstream to store these
parameters. Also, store msm_mode in connector_state to be accessed
in commit path.

Change-Id: Ia5bdebe75f00aa15fb7db4dc3a0d50c30894a95c
Signed-off-by: Orion Brody <obrody@codeaurora.org>
2021-01-04 13:18:36 -08:00
Samantha Tran
790eda032e disp: msm: drmP.h removed, add new headers
Commit ("drm: delete drmP.h + drm_os_linux.h") removes the
drmP header file. This changes updates the msm driver
by adding the individually required header files.

Change-Id: I360aa028c2ce75317d33da988b36164041177014
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2020-12-17 09:50:47 -05:00
qctecmdr
a2a3c5e864 Merge "disp: msm: sde: cache encoder_mask for vblank_work" 2020-11-24 06:44:04 -08:00
Abhijit Kulkarni
fef65e7b8c disp: msm: sde: reset sw state on vm transition
This change resets the plane and crtc dirty properties on
transition to other VM. This ensures when the VM acquires the
hw again all these properties on the new state are reapplied.

Change-Id: Id95676453eb9ae937b1b22f0e244b47449101cb0
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-11-18 14:37:04 -08:00
Steve Cohen
aa064ada86 disp: msm: sde: cache encoder_mask for vblank_work
There is a race between disable commit swap-state on display
thread and vblank work on event thread which may skip applying
the vblank vote if the encoder_mask has already been cleared.
To avoid the race, use a cached encoder_mask that is gauranteed
to be valid between the vblank_on and vblank_off calls.

Also, vblank queue work is initializing a variable that's never
used and msm_disable_outputs has 2 instances of pointers to old
CRTC state. Remove this dead code.

Change-Id: I5e4a482b8f067e272a2aef5afa08cc0e1ab89434
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2020-11-17 17:24:30 -05:00
qctecmdr
8f16ccc93b Merge "disp: msm: add support to notify retire frame event" 2020-09-21 03:57:31 -07:00
Lei Chen
c44e0b42df disp: msm: check max FPS of DFPS to update UIDLE configurations
It is not applicable for all DFPS cases to update UIDLE state
according to current frame rate. If DFPS changes frame rate
through vertical front porch values, the SDE clocks and transfer
time will not get changed accordingly, and it always get fixed
at max frame rate configuration of DFPS.
Add this change to check max FPS of DFPS instead of current
frame rate for UIDLE update, if DFPS is enabled with VFP.

Change-Id: I7634bce6a9eb1af212ba19a267735be08b20ae1f
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
2020-09-15 09:51:30 +08:00
Raviteja Tamatam
e3f6420cee disp: msm: add support to notify retire frame event
Added sysfs entry on crtc to notify a retire frame event
which indicates start of new frame. It is added at same
time of signaling retire fence.

Change-Id: Ie60aae96bd6e6bfb3cfe9db482cb59053f22383f
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
2020-09-08 02:12:28 +05:30
Gopikrishnaiah Anandan
10e00393d8 drm: msm: add dspp caps blob to crtc
All sde crtc's are virtual when they are created. Resources for the crtc
is allocated when crtc is enabled. All crtc's will not have same
capabilities because some of the dspp blocks have additional hardware
blocks. Change exposes additional dspp capabilities dynamically when
crtc is allocated the dspp hardware block.

Change-Id: I93e76a1335574e4ca30d9419ef6cc6e8149e2c3c
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
2020-08-31 14:37:30 -07:00
Narendra Muppalla
2c2a06abba disp: msm: sde: reconfigure misr based on user input
In current SDE driver when misr is enabled, for each commit in
encoder kickoff stage misr is configured for both lm and interface
misr blks. This can clear misr data before client could collect misr.
This change avoids misr data clear and configures misr based on
user input.

Change-Id: I85fc19c78afc6d01346219250c82f2ada824eb0d
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
2020-07-14 18:06:14 -07:00
Jeykumar Sankaran
8b032e5e46 disp: sde: add CRTC property for VM requests
Add a CRTC property to request the VM to acquire/release
HW resources.

Display driver in trusted VM boots up without HW ownership. Set
the default value of the property as RELEASED to handle resource
assignments.

Change-Id: Iea651a2fea902d95d4b954052af4ef016af15a91
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
2020-06-19 17:46:43 -07:00
Krishna Manikandan
5541a20748 disp: msm: sde: modify check for active datapaths
In some cases like suspend and cwb concurrencies,
the number of mixers in the sde_crtc structure
can become zero. Add support to get the number
of mixers from topology in those cases to
avoid incorrect resource allocation request.

Change-Id: Id9b82e805ff50a107ad06514b4e41c0917abdf33
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
2020-05-08 13:48:49 -04:00
Amine Najahi
4fef803aff disp: msm: sde: increase max number of mixers to 4
Increase the maximum number of mixers per crtc to 4 to
support 4LM use case. This change also increases the number
of data path to 4 to support 4LM in continuous splash handoff.

Change-Id: I4655017dcb405fad69513bebb8fd7f848fc5873d
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
2020-05-06 14:16:31 -04:00
Amine Najahi
89c7e1dadf disp: msm: sde: add plane staging management for 4LM topologies
When a 4LM topology is used each plane attached to a CRTC
is tagged with a L/R layout value and an offset value
depending on where destination X coordinate lands on the display.
The layout information is used to determine SSPP to LM
pair mapping and local coordinate space.

This change also handles source-split and Z-order
validation checks for planes staged on different mixer
pairs.

Change-Id: I1b20223388e65fc36a8b379ad9df23a277fcd1a5
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
2020-05-05 23:06:39 -04:00
Steve Cohen
b9e3d4aebb disp: msm: sde: decouple FETCH_PIPE_ACTIVE logic from setup_blendstages
Setup blendstages is done per LM but FETCH_PIPE_ACTIVE is per CTL.
Overloading mixer blendstage setup with fetch pipe logic can lead
to HW programming errors. Refactor the logic for setting
FETCH_PIPE_ACTIVE by adding a new op that allows caller to provide
a bitmask of all pipes required to be active on this CTL. This new
logic includes support for:
 - 4LM use-cases, staging pipes for all LMs within a CRTC
 - Demura fetch-pipe without need for tracking via active_cfg (removed)

Also, lower the cyclomatic complexity in setup_blendstages by moving
the logic for obtaining the mixer config settings in to a helper
function.

Change-Id: I2907b359ffad5734be5b06f44919b5ddb1ef3f7c
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2020-05-04 19:47:00 -07:00
qctecmdr
dfc3e3ddc8 Merge "disp: msm: sde: add sys cache usage for static image" 2020-05-01 17:58:07 -07:00
Nilaan Gunabalachandran
83ee51cb5a disp: msm: sde: add sys cache usage for static image
Store full or partial static image in system cache (L3 cache)
for video mode primary display. Added additional commit to
crtc commit thread to transition to read cache state.
The change also updates llcc APIs to support generic functionality.

Change-Id: I6b2a45da946d7e0e0b326da9d214be3f01a9420e
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2020-04-27 15:12:17 -04:00
qctecmdr
e689a13372 Merge "drm/msm: avoid dim layer setup if not required" 2020-04-23 12:07:39 -07:00
Samantha Tran
5217dfd7ea disp: msm: sde: update QoS values on FPS switch
This change updates plane's dirty flag with QoS
value to ensure QoS gets reprogrammed with new FPS
settings. This is required as QoS values will change
with FPS.

Change-Id: I377b99da2a640d375bd48477f149197b332e7f7b
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2020-04-21 12:48:23 -07:00
Adrian Salido
51769fd40f drm/msm: avoid dim layer setup if not required
Dim layer clearing/setup requires reading registers in order to update
value, doing this add additional CPU processing when it's not really
needed. Add logic to only do the updates only when needed.

Bug: 142504774
Change-Id: I23bcbe39575de35c387cfb7d2b9dc993525e4f98
Signed-off-by: Adrian Salido <salidoa@google.com>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2020-04-21 12:30:28 -07:00
Samantha Tran
7401ef1995 disp: msm: sde: correct line time to include compression ratio
Current computation of line time does not include compression ratio
from either DSC or VDC. This change stores source bpp and target bpp in
sde_crtc during sde encoder mode set to be used while calculating line
time.

Change-Id: Ib1e045dce17fcf006447d4562b402cc3f214ed8c
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2020-04-10 16:23:38 -07:00
qctecmdr
76d89c1e24 Merge "disp: msm: add support for no blend planes" 2020-04-01 17:45:16 -07:00
Gopikrishnaiah Anandan
078d42797b disp: msm: add support for no blend planes
Some of the features in the DPU hardware needs planes to be staged but
it should not be blended in the layer mixer. Change adds support for drm
driver client to set the blend type on the plane and updates driver code
to skip staging the plane.

Change-Id: I1e8c7f6ce5617820ea8b24419e0d4d27b481819b
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
2020-03-31 14:07:49 -07:00
Prabhanjan Kandula
eed1c6df2c disp: msm: sde: enable pu checks only if main feature is set
This change fixes feature specific partial update checks in
atomic check by enabling partial update specific features only if
respective core feature is enabled.

Change-Id: If3678a52fa0f8d9e1d714a662601e5628e1637d2
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
2020-03-30 10:30:49 -07:00
Veera Sundaram Sankaran
bceea4e1fe disp: msm: sde: reset ctl on autorefresh disable failure
Reset MDP ctl path and DSI ctl on autorefresh
disable failure. This will enable the hardware
to recover from the hang.

Change-Id: Ia9acc8573c22e0713179ef4f6ef604caacabfadb
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2020-03-28 23:07:32 -07:00
Amine Najahi
d26c9811ca disp: msm: sde: add partial update handling in cp framework
Add partial update handling for color processing features.
This will validate and set cp features for each frame if
applicable.

Change-Id: Id78c1f4ecbd74781c0c03c04efb528d6a8b91264
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
2020-01-31 07:51:54 -08:00
Abhijit Kulkarni
dc8e0291e4 disp: msm: sde: move dsc implementation to a new file
This change moves the DSC implementation into a separate file.
This is required to add support for new compression algorithms.
This cleanup change also, moves struct sde_encoder_virt
declaration to the encoder header file.

Change-Id: Idc3b96e65fcce2a7ee6e17af604cec0cb574f6f7
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-01-22 12:30:43 -08:00
Jayaprakash
ad40a300a1 disp: msm: sde: allow qsync support along with VRR
Allow Qsync and VRR features to be supported independently
by display driver. Restrict the feature availability in
same composition cycle.

Change-Id: I696eb72a2b4f9451e142ffdc5acccc8987c36b6d
Signed-off-by: Kalyan Thota <kalyant@codeaurora.org>
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
2019-10-17 17:07:33 +05:30
Veera Sundaram Sankaran
b7ba56ff00 disp: msm: sde: fix inline rotator downscale ratio check
During the validation of inline-rotator downscale ratio,
in the plane atomic_check phase, the client_type is
derived from the crtc->state. This leads to wrong
client_type as in check phase, it has to be derived
from the new crtc state. Fix it to derive from
new crtc, which would in turn be used to get the
correct inline-rotator downscale ratio.

Change-Id: I109fc6fd81182b1cda1c4feefbf421d3fab433c7
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2019-09-18 13:28:17 -07:00
Veera Sundaram Sankaran
f61e5545d7 disp: msm: sde: fix crtc client type checks for WB
CRTC client type is wrongly identified as RT_CLIENT
for WB as the API considers only RT and RT_RSC. Resolve
it by adding a new API to check for RT CTRC.

Change-Id: I1f216f60a18215426e594d0f8b09852af376799d
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2019-07-24 14:52:42 -07:00
Lakshmi Narayana Kalavala
99a7f030d4 disp: msm: sde: fix the QOS setting mismatch
Currently the display driver does not consider the write back
client while deriving client type for QOS settings.
Add new API to consider the write back and other non
real time clients also for picking up the proper QOS settings.
This patch also fixes the QOS setting mismatch with QSEEDLITE
hardware.

Change-Id: I5db3d21921b8930bb6399ea355d3ce2b60e51430
Signed-off-by: Lakshmi Narayana Kalavala <lkalaval@codeaurora.org>
2019-07-09 13:47:26 -07:00
Lakshmi Narayana Kalavala
70486d209c disp: msm: sde: remove vblank cache logic
Userspace is not supposed to request vblank until crtc is enabled,
because drm framework rejects the request if crtc is not enabled.
Any vblank request prior to that need to be cached in the userspace.
Hence removing the cache logic from the downstream driver.

Change-Id: I78ceee331cba2d691f68fd649bd5cf33f7868e72
Signed-off-by: Lakshmi Narayana Kalavala <lkalaval@codeaurora.org>
2019-05-30 16:22:59 -07:00
qctecmdr
9c05197ef9 Merge "disp: msm: sde: use wr_ptr interrupt instead of ctl_start" 2019-05-24 09:38:19 -07:00
Samantha Tran
3be27eafcc disp: msm: snapshot of msm and sde driver
This snapshot ports changes from 4.14 to 4.19 into
the msm and sde layer. Snapshot was taken as of
commit 0f8fb25421ff ("cnss2: Add device version to
SOC info structure").

Change-Id: I59b799a78319c2db6930a2a10bc38976f8c09898
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2019-05-22 13:08:31 -07:00
Manoj Kumar AVM
7fc5e5d45f Revert "disp: msm: sde: remove vblank cache logic"
This reverts commit e6754ef40a.

Change-Id: If5921c6428b2b79ae5979d782138f10e4673d1fb
Signed-off-by: Manoj Kumar AVM <manojavm@codeaurora.org>
2019-05-21 18:33:28 -07:00
qctecmdr
e6933ff2dc Merge "disp: msm: sde: remove vblank cache logic" 2019-05-05 21:21:19 -07:00
Lakshmi Narayana Kalavala
e6754ef40a disp: msm: sde: remove vblank cache logic
Userspace is not supposed to request vblank until crtc is enabled,
because drm framework rejects the request if crtc is not enabled.
Any vblank request prior to that need to be cached in the userspace.
Hence removing the cache logic from the downstream driver.

Change-Id: I5383e39075377e3e49b8d335598ddfa48ab54666
Signed-off-by: Lakshmi Narayana Kalavala <lkalaval@codeaurora.org>
2019-04-26 17:29:59 -07:00
Dhaval Patel
a74d2cf7fa disp: msm: add runtime_pm ops support in drm driver
Add runtime_pm ops support in drm driver instead
of direct sde_power_resource_enable/disable call.
It allows drm driver to use runtime pm refcount logic
to track the resources instead of custom implementation.
The change also removes the NRT_CLIENT support from
sde_power_handle code to simplify it further.

Change-Id: Ib14692dca5876703d0a230da2512d731b69b8ebb
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2019-04-24 13:27:48 -07:00
Narendra Muppalla
3709853456 Display drivers kernel project initial snapshot
This change brings msm display driver including sde,
dp, dsi, rotator, dsi pll and dp pll from base 4.19 kernel
project. It is first source code snapshot from base kernel project.

Change-Id: Iec864c064ce5ea04e170f24414c728684002f284
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
2019-04-14 22:20:59 -07:00