提交图

67 次代码提交

作者 SHA1 备注 提交日期
qctecmdr
6bf96605eb Merge "disp: msm: sde: cache disable cp properties during last close" 2021-08-03 19:17:54 -07:00
Gopikrishnaiah Anandan
610b71feb9 disp: msm: sde: cache disable cp properties during last close
When all instances of driver fd's are closed by user-space client, drm driver
will be closed. When last close of driver is called, custom reset properties
api will be called where driver should cache the properties that it wants to
clear. Current behavior of color processing driver is to clear hardware
configuration instead of caching which can cause crashes if clocks are off.
Change updates the driver to cache the pending disable and update hardware
during display commit.

Change-Id: I9703f860ed0ae3c859d6fc3995b58be13203f259
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
2021-07-29 13:56:02 -07:00
Steve Cohen
a42fd877c7 disp: msm: sde: cancel delayed work items during TUI transition
Delayed work items may touch HW registers. If these work items
run while HW is not owned by this VM it will lead to invalid
access. This happens in video mode as HAL does not disable idle
power-collapse in this mode. It can also happen with ESD status
if lastclose or TUI transition failure occurs.

Although there is a contract with user mode to turn off certain
features, kernel cannot rely on it to always do the right thing.
Prevent potential crashes from certain corner cases by
cancelling all delayed work items when the HW ownership is
transferred.

Change-Id: I08da17f2ce72bf2fddf71924c3e8edd2e2715be8
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2021-07-16 20:45:42 -04:00
qctecmdr
a5da9d0045 Merge "disp: msm: sde: remove fb's attached to a drm_file in preclose" 2021-07-15 13:14:46 -07:00
qctecmdr
a44120edf1 Merge "disp: msm: sde: correct num_datapath during PM resume with CWB" 2021-07-15 13:14:46 -07:00
qctecmdr
e32c87abbe Merge "disp: msm: sde: modify in_clone_mode after wb_reset is done" 2021-07-15 13:14:46 -07:00
Jayaprakash Madisetty
436efb403c disp: msm: sde: modify in_clone_mode after wb_reset is done
Add changes to modify the phys_enc->in_clone_mode variable
post wb_reset_state since this is a shared variable used
during atomic_check and atomic_commit. In current issue case,
wb_atomic_check has set in_clone_mode to true in commit N,
and in commit N-1 CWB is being disabled and re-sets the
in_clone_mode variable to false causing pp_done timeouts in
primary in commit N.

Change-Id: I8159bbdb5622a351d76bdc4dba75d48df20f4365
Signed-off-by: Jayaprakash Madisetty <jmadiset@codeaurora.org>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2021-07-14 13:43:21 -07:00
Jayaprakash Madisetty
a29369e224 disp: msm: sde: correct num_datapath during PM resume with CWB
In PM resume with CWB concurrency usecase, crtc pointer in
conn->state is NULL since drm_mode_config_reset operation is
performed on pm_resume. This change relies on conn_mask in
new_crtc_state for primary connector retrieval and also adds
get_num_lm_from_mode callback to DSI for LM count retrieval
from dsi panel topology. Existing get_mode_info api cannot
retrieve the topology info because mode->priv_info is NULL.
This occurs as WB encoder is added in the drm encoder_list
before primary encoder, introduced as part of commit d28ebf05f4
("disp: msm: sde: populate WB display encoder list before dsi").

Change-Id: I55358fd88ab778bd81475cf3628be13335de1cb5
Signed-off-by: Jayaprakash Madisetty <jmadiset@codeaurora.org>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2021-07-09 09:12:26 -07:00
Yashwanth
ddd671b0d7 disp: msm: sde: reset dim layer dirty prop during idle pc
During idle power collapse, dim layer dirty flags are
stored in sde_crtc_state which might be invalid if state
swap occurs. This change adds revalidate mask in sde_crtc
structure to revalidate after coming out of idle power
collapse.

Change-Id: Ie2f34a794896a3f8e729ef7d1f3ae35340123257
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2021-07-08 10:24:48 -07:00
Jayaprakash Madisetty
0e3d422520 disp: msm: sde: remove fb's attached to a drm_file in preclose
This change avoids upstream drm issuing drm_atomic_commit in
drm_fb_release which is leading to artifacts on screen or
atomic_check failures due to atomically unstaging each fb
from plane_state and committing remaining planes on hardware.

 a) This patch moves the state operations for setting crtc to
    connector state to a helper api.
 b) This patch clears any dim_layers present in the crtc_state
    as part of null commit.
 c) This patch removes any framebuffers attached to a drm_file
    in msm_preclose whose refcount is not managed by composer kill
    inadvertently and issues null flush to hardware in such cases.
 d) This patch handles msm_preclose as part of msm_release
    operation since legacy feature is not supported
    for msm_driver.

Change-Id: Ib2068d74d4b23b73b7c84544858c9f6bb6adfa67
Signed-off-by: Jayaprakash Madisetty <jmadiset@codeaurora.org>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2021-07-08 10:24:32 -07:00
qctecmdr
8bbc6f2698 Merge "disp: msm: sde: flush commit thread queue during pm suspend" 2021-06-01 20:21:34 -07:00
Yashwanth
75f3403326 disp: msm: sde: add kickoff_in_progress flag in sde crtc
In dual display usecases, during pm suspend/resume,
commit is scheduled only on primary crtc thread. If idle
timeout value is very short such as in LP2 mode, it might
result in race condition due to idle pc off work getting
scheduled on its crtc thread. This change adds kickoff in
progress flag to handle such cases as crtc frame pending
count is only updated after rc kickoff.

Change-Id: Iebb331d914b23cc5eeadfeb2a488891e88b3202a
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2021-05-19 16:35:40 -04:00
Yashwanth
8e53d758dd disp: msm: sde: add ctl reset during wait for commit done timeout
During one of the DP timeout usecases, flush doesn't take
effect due to vid vblank wait failure. As a result, smmu
faults are observed because of fetching the previously
staged planes. This change adds ctl reset in the same
DP atomic commit context to recover and avoid
smmu faults.

Change-Id: I2f9aceca56e27f140607317f7596d6fe0d908af8
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2021-05-19 16:35:40 -04:00
Ping Li
9dc60208de disp: msm: sde: handle LTM switch in and out of dual pipe merge mode
When LTM is switching on/off, merge_mode bit value gets toggled between
0x1 (dual pipe merge configuration) and 0x0 (single pipe configuration).
It is illegal to reconfigure LTM to/from dual-pipe merge mode before
both LTM instances have completed their current workloads. This change
adds support to disable merge_mode one frame after histogram is disabled
to make sure both hardware instances are completely idle and avoid
corrupted histogram data collection.

Change-Id: I9a6b5cbfb69e8af7936749e57fe7c8f7c2703b95
Signed-off-by: Ping Li <pingli@codeaurora.org>
2021-05-12 22:28:53 -07:00
Nilaan Gunabalachandran
c5835a215e disp: msm: sde: frame data feature
Add support to send a data packet of info, written to
predefined buffers, providing information about each submitted frame.
Add required UAPI definitions for frame data buffers and event
notification.
Add support to read ubwc statistics from hw, based on defined rois.

Change-Id: I51f279de98ae4e2a02b0df6943d334764011d5db
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2021-04-06 08:49:49 -04:00
qctecmdr
133fc8a6e8 Merge "disp: msm: sde: fix potential race condition" 2021-04-01 11:12:09 -07:00
Ping Li
7ed51b95a2 disp: msm: sde: fix potential race condition
Move the hist irq handling out of callback function, i.e., the hw
interrupt irq_lock context, to avoid dead lock between crtc spin_lock
and irq_lock. This change also extends crtc spin_lock coverage in
_sde_cp_crtc_enable_hist_irq to prevent null pointer dereference on
event node, which can be deleted during crtc event de-registration.

Change-Id: Iadaed54ab93c4c4abe065a8762d2addccb0c65c6
Signed-off-by: Ping Li <pingli@codeaurora.org>
2021-03-31 16:07:40 -07:00
Narendra Muppalla
21f527d47d disp: msm: sde: use different spin lock for frame events
Due to lock sequence inconsistency between sde_crtc->spin_lock and
sde_kms->hw_intr->irq_lock can cause deadlock, to avoid this possible
deadlock this change uses different spin lock for frame events.

Change-Id: I51b1184dfa1069c87653099b95b992b277721daf
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
2021-03-31 15:02:14 -07:00
Dhaval Patel
b5cde14bca disp: msm: sde: calculate line_time once during modeset
Calculate line_time once during modeset and allow
each plane to use it instead of calculating for each frame.
It also simplifies the line_time calculation for
command mode display.

Change-Id: I94ce29eec94bfdbee9016fbf93378661ebf79c03
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2021-03-18 15:03:30 -07:00
Gopikrishnaiah Anandan
1d39b8a5a9 disp: msm: sde: add checks for hfc feature enablement of demura
HFC feature of demura needs a skip blend plane to be set. If skip blend
plane is not set and HFC feature is requested to be enabled, driver
should skip turning on HFC demura feature. Change adds checks to ensure
that HFC is always enabled with skip blend plane staged.

Change-Id: I923359c7cb143867660b4c1e667f56ed42fa51c9
2021-03-17 11:22:08 -07:00
Gopikrishnaiah Anandan
d9187ba0d9 disp: msm: sde: stop crtc features during encoder disable
Encoder is disabling planes and unstaging layers from layer mixer. Some
of the crtc features are dependent on the plane being staged. Change
adds api that encoder can call on crtc to stop the features that are
dependent on source pipes.

Change-Id: I4d875155ceb8f66acfe6ce0096141ca7253bb140
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
2021-03-17 11:22:08 -07:00
Christopher Braga
db39b61a5f disp: msm: sde: populate DRM pipeline setup during cont-splash
Declare the continuous splash pipeline setup to userspace by filling
in the DRM states for all plane, crtc, encoder, and connector objects
in use. This information will be treated as an 'informative' state,
and will be cleared at the start of the first commit to maintain
the DRM methodology of DRM clients being the only controller of
the pipeline. This ensures any configuration provided by userspace
is accepted and applied, even if it may already align with the setup
done by continuous splash.

This DRM state configuration is done via manual modification of the
DRM object states. Modification via the exposed DRM UAPI functions
is not possible due to no drm_atomic_state object linking the DRM
pipeline objects together.

Change-Id: I67650e05aafbb4e799cf60939f0595bc3786fc6e
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
2021-03-17 11:22:07 -07:00
Christopher Braga
87e6558847 disp: msm: sde: cleanup naming in sde_color_processing
As the number of cp features has continued to grow, the file
sde_color_processing has become increasingly harder to parse.
Update function and parameter names to better identify internal
functions and increase readability.

Change-Id: Ib82d6c9a45b36b932ab3a2d573b7cbe13a6c10bc
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
2021-03-17 11:22:07 -07:00
Gopikrishnaiah Anandan
320ae88cf1 disp: msm: sde: avoid caching color processing properties in validate
Recent investigation shows that color processing properties are
incorrectly being cached in validate. This can result in unwanted
color processing properties being applied if a previous commit
failed or was validate only.

Add color processing properties to sde crtc state instead of marking
them dirty in color processing driver. When atomic commit is called
properties from state will be marked as dirty and applied.

Change-Id: If231a1f028e4cbd0b50eb0a947f4d58f94390a0c
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
2021-03-17 11:22:07 -07:00
Nilaan Gunabalachandran
8e2e3358d6 Revert "disp: msm: sde: Avoid kcallocs in atomic commit path"
This reverts commit 6886d03e4a.
It tries to memset the pstate from UI thread (crtc atomic check)
and crtc commit thread.

Change-Id: Ic9d3e5555d7085832df76025e53488d2b3365739
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2021-03-02 09:06:22 -05:00
Gopikrishnaiah Anandan
e7c7283510 disp: msm: sde: add support for noise layer
DPU has added support for noise injection into the layer stack. Change
adds support for noise layer programming and exposes the hardware block
to the user space modules.

Change-Id: Id176eea54fcdcd5d399457b14133a1ccde07299f
2021-02-23 15:56:36 -08:00
Chandan Uddaraju
4fe3d97078 sde: wb: add changes to support Dedicated-CWB
Add new capture/tap point as CRTC property for
D-CWB feature. Update the hardware blocks and
corresponding APIs to configure D-CWB data path.
Add new hardware pingpong blocks that
are dedicated for CWB.

Change-Id: I22576df1768b50f9f47d8527f62913b01ff4d9a7
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
2021-02-19 12:52:59 -08:00
Samantha Tran
6886d03e4a disp: msm: sde: Avoid kcallocs in atomic commit path
To avoid kcalloc for the multirect plane states and plane states will now
be stored sde crtc. These states are populated momentarily and accessed in
a single context for a handful of functions then are not used. This will
clean up parameters passed between functions in the commit path as well.

Change-Id: I6a8116a43c140b3f1c0464734032b8db13c1cfb0
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2021-01-28 08:04:08 -08:00
orion brody
d00d481360 disp: msm: move from drm_mode to msm_mode
Move away from the private and private_flags fields from drm_mode,
as it is being deprecated in latest kernel version. Instead, Add
msm_display_mode as a wrapper to be used in downstream to store these
parameters. Also, store msm_mode in connector_state to be accessed
in commit path.

Change-Id: Ia5bdebe75f00aa15fb7db4dc3a0d50c30894a95c
Signed-off-by: Orion Brody <obrody@codeaurora.org>
2021-01-04 13:18:36 -08:00
Samantha Tran
790eda032e disp: msm: drmP.h removed, add new headers
Commit ("drm: delete drmP.h + drm_os_linux.h") removes the
drmP header file. This changes updates the msm driver
by adding the individually required header files.

Change-Id: I360aa028c2ce75317d33da988b36164041177014
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2020-12-17 09:50:47 -05:00
qctecmdr
a2a3c5e864 Merge "disp: msm: sde: cache encoder_mask for vblank_work" 2020-11-24 06:44:04 -08:00
Abhijit Kulkarni
fef65e7b8c disp: msm: sde: reset sw state on vm transition
This change resets the plane and crtc dirty properties on
transition to other VM. This ensures when the VM acquires the
hw again all these properties on the new state are reapplied.

Change-Id: Id95676453eb9ae937b1b22f0e244b47449101cb0
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2020-11-18 14:37:04 -08:00
Steve Cohen
aa064ada86 disp: msm: sde: cache encoder_mask for vblank_work
There is a race between disable commit swap-state on display
thread and vblank work on event thread which may skip applying
the vblank vote if the encoder_mask has already been cleared.
To avoid the race, use a cached encoder_mask that is gauranteed
to be valid between the vblank_on and vblank_off calls.

Also, vblank queue work is initializing a variable that's never
used and msm_disable_outputs has 2 instances of pointers to old
CRTC state. Remove this dead code.

Change-Id: I5e4a482b8f067e272a2aef5afa08cc0e1ab89434
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2020-11-17 17:24:30 -05:00
qctecmdr
8f16ccc93b Merge "disp: msm: add support to notify retire frame event" 2020-09-21 03:57:31 -07:00
Lei Chen
c44e0b42df disp: msm: check max FPS of DFPS to update UIDLE configurations
It is not applicable for all DFPS cases to update UIDLE state
according to current frame rate. If DFPS changes frame rate
through vertical front porch values, the SDE clocks and transfer
time will not get changed accordingly, and it always get fixed
at max frame rate configuration of DFPS.
Add this change to check max FPS of DFPS instead of current
frame rate for UIDLE update, if DFPS is enabled with VFP.

Change-Id: I7634bce6a9eb1af212ba19a267735be08b20ae1f
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
2020-09-15 09:51:30 +08:00
Raviteja Tamatam
e3f6420cee disp: msm: add support to notify retire frame event
Added sysfs entry on crtc to notify a retire frame event
which indicates start of new frame. It is added at same
time of signaling retire fence.

Change-Id: Ie60aae96bd6e6bfb3cfe9db482cb59053f22383f
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
2020-09-08 02:12:28 +05:30
Gopikrishnaiah Anandan
10e00393d8 drm: msm: add dspp caps blob to crtc
All sde crtc's are virtual when they are created. Resources for the crtc
is allocated when crtc is enabled. All crtc's will not have same
capabilities because some of the dspp blocks have additional hardware
blocks. Change exposes additional dspp capabilities dynamically when
crtc is allocated the dspp hardware block.

Change-Id: I93e76a1335574e4ca30d9419ef6cc6e8149e2c3c
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
2020-08-31 14:37:30 -07:00
Narendra Muppalla
2c2a06abba disp: msm: sde: reconfigure misr based on user input
In current SDE driver when misr is enabled, for each commit in
encoder kickoff stage misr is configured for both lm and interface
misr blks. This can clear misr data before client could collect misr.
This change avoids misr data clear and configures misr based on
user input.

Change-Id: I85fc19c78afc6d01346219250c82f2ada824eb0d
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
2020-07-14 18:06:14 -07:00
Jeykumar Sankaran
8b032e5e46 disp: sde: add CRTC property for VM requests
Add a CRTC property to request the VM to acquire/release
HW resources.

Display driver in trusted VM boots up without HW ownership. Set
the default value of the property as RELEASED to handle resource
assignments.

Change-Id: Iea651a2fea902d95d4b954052af4ef016af15a91
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
2020-06-19 17:46:43 -07:00
Krishna Manikandan
5541a20748 disp: msm: sde: modify check for active datapaths
In some cases like suspend and cwb concurrencies,
the number of mixers in the sde_crtc structure
can become zero. Add support to get the number
of mixers from topology in those cases to
avoid incorrect resource allocation request.

Change-Id: Id9b82e805ff50a107ad06514b4e41c0917abdf33
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
2020-05-08 13:48:49 -04:00
Amine Najahi
4fef803aff disp: msm: sde: increase max number of mixers to 4
Increase the maximum number of mixers per crtc to 4 to
support 4LM use case. This change also increases the number
of data path to 4 to support 4LM in continuous splash handoff.

Change-Id: I4655017dcb405fad69513bebb8fd7f848fc5873d
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
2020-05-06 14:16:31 -04:00
Amine Najahi
89c7e1dadf disp: msm: sde: add plane staging management for 4LM topologies
When a 4LM topology is used each plane attached to a CRTC
is tagged with a L/R layout value and an offset value
depending on where destination X coordinate lands on the display.
The layout information is used to determine SSPP to LM
pair mapping and local coordinate space.

This change also handles source-split and Z-order
validation checks for planes staged on different mixer
pairs.

Change-Id: I1b20223388e65fc36a8b379ad9df23a277fcd1a5
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
2020-05-05 23:06:39 -04:00
Steve Cohen
b9e3d4aebb disp: msm: sde: decouple FETCH_PIPE_ACTIVE logic from setup_blendstages
Setup blendstages is done per LM but FETCH_PIPE_ACTIVE is per CTL.
Overloading mixer blendstage setup with fetch pipe logic can lead
to HW programming errors. Refactor the logic for setting
FETCH_PIPE_ACTIVE by adding a new op that allows caller to provide
a bitmask of all pipes required to be active on this CTL. This new
logic includes support for:
 - 4LM use-cases, staging pipes for all LMs within a CRTC
 - Demura fetch-pipe without need for tracking via active_cfg (removed)

Also, lower the cyclomatic complexity in setup_blendstages by moving
the logic for obtaining the mixer config settings in to a helper
function.

Change-Id: I2907b359ffad5734be5b06f44919b5ddb1ef3f7c
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2020-05-04 19:47:00 -07:00
qctecmdr
dfc3e3ddc8 Merge "disp: msm: sde: add sys cache usage for static image" 2020-05-01 17:58:07 -07:00
Nilaan Gunabalachandran
83ee51cb5a disp: msm: sde: add sys cache usage for static image
Store full or partial static image in system cache (L3 cache)
for video mode primary display. Added additional commit to
crtc commit thread to transition to read cache state.
The change also updates llcc APIs to support generic functionality.

Change-Id: I6b2a45da946d7e0e0b326da9d214be3f01a9420e
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2020-04-27 15:12:17 -04:00
qctecmdr
e689a13372 Merge "drm/msm: avoid dim layer setup if not required" 2020-04-23 12:07:39 -07:00
Samantha Tran
5217dfd7ea disp: msm: sde: update QoS values on FPS switch
This change updates plane's dirty flag with QoS
value to ensure QoS gets reprogrammed with new FPS
settings. This is required as QoS values will change
with FPS.

Change-Id: I377b99da2a640d375bd48477f149197b332e7f7b
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2020-04-21 12:48:23 -07:00
Adrian Salido
51769fd40f drm/msm: avoid dim layer setup if not required
Dim layer clearing/setup requires reading registers in order to update
value, doing this add additional CPU processing when it's not really
needed. Add logic to only do the updates only when needed.

Bug: 142504774
Change-Id: I23bcbe39575de35c387cfb7d2b9dc993525e4f98
Signed-off-by: Adrian Salido <salidoa@google.com>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2020-04-21 12:30:28 -07:00
Samantha Tran
7401ef1995 disp: msm: sde: correct line time to include compression ratio
Current computation of line time does not include compression ratio
from either DSC or VDC. This change stores source bpp and target bpp in
sde_crtc during sde encoder mode set to be used while calculating line
time.

Change-Id: Ib1e045dce17fcf006447d4562b402cc3f214ed8c
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2020-04-10 16:23:38 -07:00
qctecmdr
76d89c1e24 Merge "disp: msm: add support for no blend planes" 2020-04-01 17:45:16 -07:00