نمودار کامیت

246 کامیت‌ها

مولف SHA1 پیام تاریخ
Steve Cohen
7f0c843da4 disp: msm: sde: move boolean flags in catalog to a bitmap
Move all the individual boolean flags from HW catalog into a
"features" bitmap. These flags are used to specify support of
various target specific features.

Change-Id: I2334b3b873f3737f91bbae4ef576408247710156
Signed-off-by: Steve Cohen <quic_cohens@quicinc.com>
2021-10-26 11:21:33 -07:00
Dhaval Patel
daa4273e02 disp: msm: sde: disable vsync_in to update tear check
Commit b67da33a6307 ("trigger tx_wait if panel
resolution switch") increases the mode switch latency.
Alternatively, single buffer tear check registers can be
updated when vsync_in is disabled. It allows mode switch
frame trigger as posted start frame trigger.

Change-Id: I8068736b2ea01f6e4160e765fc39d7fc2a8590c9
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2021-10-08 13:29:45 -07:00
qctecmdr
fba8cf7c57 Merge "disp: msm: sde: reset dsc mux config in encoder disable" 2021-10-07 21:23:56 -07:00
Prabhanjan Kandula
9e988121fc disp: msm: sde: reset dsc mux config in encoder disable
During display encoder disable, reset the dsc control
mux configuration during null commit to ensure dsc hw
blocks are cleanly freed up.

Change-Id: I02e2f074450e4d7b49dc8fec14777f380786c63e
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
2021-10-07 00:09:06 -07:00
Dhaval Patel
b696aa3b24 disp: msm: sde: trigger tx_wait if panel resolution switch
Trigger tx_wait if command mode panel resolution
switches during mode switch to avoid early single buffer
tear check programming.

Change-Id: Ib747df8250c714248a44b596c2c8aeef006ea4fc
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2021-10-04 13:16:00 -07:00
Nilaan Gunabalachandran
711eabbf43 disp: msm: sde: account for pref lm when exposing avail resources
If an external display, such as DP, requests for the available
resources, resource manager (RM) will provide a count of all unused
mixers. If the primary/secondary display(s) are not active, the RM
will report the associated preferred mixers as free resources.
However, RM will not allow preferred mixers to be allocated to other
displays. DP driver could look at these available resources and assume
a high resolution mode is possible and fail during resource allocation.

This change updates the available resources info API to account for
primary/secondary preferences while exposing available resources.

Change-Id: I134a1047f24ac9f1fcee695aa14a1d3e43c1571f
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2021-09-27 12:13:37 -04:00
Dhaval Patel
fc2226ea25 disp: msm: reset lm blend stages for missing vsync
MDSS INTF HW block does not generate vsync if controller
turns off the link clock prematurely. This leads to
frame trigger timeout and SDE driver triggers the retire
fence after 84ms to recover gracefully. A client may switch
source pipe from one CTL path to another CTL path based
on delayed retire fence. It can lead to other ctl path
hang. This can be resolved by resetting the lm blend
stages for each missing vsync frame trigger.

Change-Id: I5a6ed03afbdad83d8fd6decc593d39e04bef62e4
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2021-09-22 09:46:32 -07:00
Nilaan Gunabalachandran
95a41081eb disp: msm: sde: clear intf mux select on slave encoders
When disabling an encoder with multiple physical encoders, the
intf mux must be cleared on all interfaces. Currently only the master
physical encoder is being cleared, leading to possible DSI
underflow errors. This change ensures that the mux is cleared
on all interface blocks.

Change-Id: Idb1b96fd65545e3599100e70ace22bc3837d7233
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2021-09-17 17:11:19 -04:00
Yashwanth
6619470eb6 disp: msm: dsi: add qsync min fps val in dsi display mode priv info
In the current code for finding the qsync min fps for a
mode, entire mode list is iterated which involves acquiring
dsi display_lock. During conn tx debugfs commands, if
qsync min fps is required, we try to acquire dsi
display_lock twice which results in hang state. This change
adds qsync min fps value in dsi_display_mode_priv_info
struct in order to get the qsync fps from the
msm_display_mode present in connector state instead of
looping through all the modes to find the mode qsync fps.

Change-Id: Ifded40d1f12462bb50fc7bdafb746ae5b8d9512a
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2021-09-15 12:09:35 +05:30
qctecmdr
bb36f9fd40 Merge "disp: msm: sde: add helper to check VM hw availability" 2021-08-18 16:48:48 -07:00
qctecmdr
88877f3037 Merge "disp: msm: sde: add sde data to va minidumps" 2021-08-15 18:31:12 -07:00
qctecmdr
4ec64c1672 Merge "disp: msm: sde: compute timeouts based on refresh rate" 2021-08-13 20:50:46 -07:00
Steve Cohen
7f3b2f0a4b disp: msm: sde: add helper to check VM hw availability
Add a utility function to check if HW has been handed over to
another VM.

Change-Id: Ic36ca1e7f15f7608e69d69fc3f4e7ad40be15704
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2021-08-12 22:58:30 -04:00
qctecmdr
7ec82f88a8 Merge "disp: msm: add qsync refresh rate support per mode" 2021-08-12 14:10:43 -07:00
Steve Cohen
9690b545df disp: msm: sde: prevent custom ioctls from accessing unowned HW
Early wakeup ioctls from perf HAL driver can access display HW
registers and come as a sideband to atomic commits. Since the
atomic validate checks are not part of this code path it's
possible for HW access to occur during a trusted UI session.
Prevent this whenever the HW is not under this VM's ownership.
Also, move the VM ownership check for the register/deregister
event ioctl to cover both the CRTC and connector events since
new connector events are being added which can access HW.

Change-Id: I39660ae60e7e8f8a405e819c43ec42fbac3f492a
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2021-08-11 15:38:27 -04:00
Prabhanjan Kandula
642c86fee9 disp: msm: sde: compute timeouts based on refresh rate
Current timeout values in sde driver for vblank, kickoff and
frame complete timeouts are fixed and can be much lower than
a vsync incase of low refresh rate display. Compute timeouts
based on refresh rate for low refresh rate displays.

Change-Id: I9dda41feb15446de7451824e185321de421ad575
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
2021-08-10 14:51:41 -07:00
Lei Chen
b151e6660b disp: msm: sde: remove clearing cur_master in encoder enable function
SDE IRQ callback can run in parallel thread to modeset after removing
pp_done wait before pre_modeset.
If cur_master is cleared in encoder enable function and irq callback
is triggered at the same time, the irq callback could not be handled
properly as cur_master is NULL.
So remove clearing cur_master in encoder enable function to avoid the
race condition between modeset and irq callback.

Change-Id: I2059c699a68838b3c9f6a7dd658a35f178b18c42
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
2021-08-09 10:58:38 +08:00
Yashwanth
64b732f335 disp: msm: add qsync refresh rate support per mode
This change adds support for qsync min refresh rate per
timing mode and populates qsync min refresh rate based
on the current fps when qsync is enabled.

Change-Id: I191d1d72e95dd065c8c0b56a6100104c00c6d8f6
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2021-08-05 15:37:20 +05:30
Andhavarapu Karthik
76d171e611 disp: msm: sde: add sde data to va minidumps
VA minidumps supports to add any allocated variable or data to
minidumps. Add panic notifier and wrapper function to add
sde data to minidump va. Add event log, register log, register dumps,
debug bus and different sde variables and states info to minidump.

Change-Id: If54da0b7067df17877e4da645d82f1705baa3f6d
Signed-off-by: Andhavarapu Karthik <kartkart@codeaurora.org>
2021-07-19 16:00:57 +05:30
Steve Cohen
a42fd877c7 disp: msm: sde: cancel delayed work items during TUI transition
Delayed work items may touch HW registers. If these work items
run while HW is not owned by this VM it will lead to invalid
access. This happens in video mode as HAL does not disable idle
power-collapse in this mode. It can also happen with ESD status
if lastclose or TUI transition failure occurs.

Although there is a contract with user mode to turn off certain
features, kernel cannot rely on it to always do the right thing.
Prevent potential crashes from certain corner cases by
cancelling all delayed work items when the HW ownership is
transferred.

Change-Id: I08da17f2ce72bf2fddf71924c3e8edd2e2715be8
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2021-07-16 20:45:42 -04:00
Jayaprakash Madisetty
436efb403c disp: msm: sde: modify in_clone_mode after wb_reset is done
Add changes to modify the phys_enc->in_clone_mode variable
post wb_reset_state since this is a shared variable used
during atomic_check and atomic_commit. In current issue case,
wb_atomic_check has set in_clone_mode to true in commit N,
and in commit N-1 CWB is being disabled and re-sets the
in_clone_mode variable to false causing pp_done timeouts in
primary in commit N.

Change-Id: I8159bbdb5622a351d76bdc4dba75d48df20f4365
Signed-off-by: Jayaprakash Madisetty <jmadiset@codeaurora.org>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2021-07-14 13:43:21 -07:00
Lei Chen
79d30e7fba drm/msm/sde: add check to fix null pointer dereference
Check if sde_enc->crtc exists before using the variable
to avoid possible NULL dereferences.

Change-Id: If7b56c3b3ad3525b3efc22b6536a2dc5c865da48
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
2021-07-07 23:04:45 -07:00
Lei Chen
be82344413 disp: msm: sde: remove unused variable topology from sde_encoder
Topology in sde_encoder is no longer used, so remove this
variable from sde_encoder.

Change-Id: Iba02ae690d81d39252d0df83882a72e35f2916ec
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
2021-06-29 14:17:59 +08:00
qctecmdr
4f79a6ceef Merge "disp: msm: sde: cancel delayed_off_work before reinitialization" 2021-06-09 10:00:48 -07:00
Lei Chen
9d4d003e30 disp: msm: sde: cancel delayed_off_work before reinitialization
Canceling delayed_off_work in encoder pre_modeset might not be
executed in all cases, but the following encoder enable might
initialize the work.
This will lead to list corruption as delayed_off work list node
is reinitialized before removing from linked list.
Move canceling delayed_off_work to start of encoder mode_set to
ensure work is canceled before reinitialization.

Change-Id: I38687604f2eedced308ea02019c162022725534e
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
2021-06-07 17:03:31 +08:00
qctecmdr
97b1db8547 Merge "disp: msm: sde: set watchdog TE when panel fails ESD check" 2021-06-04 13:29:20 -07:00
Samantha Tran
11f2efbe16 disp: msm: sde: set watchdog TE when panel fails ESD check
In the event of panel dead scenario, it is possible to receive a
mode set call before the panel has recovered. When this happens,
display should select watchdog TE as the vsync source.

Similarly when detecting a write pointer timeout, if the panel is
dead then watchdog TE should be or has already been configured and
display should not make a change to this vsync selection.

Change-Id: I732c75e54d734b00889151b914b0749ae1f27d08
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2021-06-04 09:59:44 -07:00
qctecmdr
028a432785 Merge "disp: msm: sde: update perf cpu dma latency votes on idle in video mode" 2021-06-04 09:24:46 -07:00
qctecmdr
ce2c7ef6f3 Merge "disp: msm: sde: disable RSC solver mode during HFR cases" 2021-06-02 15:18:00 -07:00
qctecmdr
8bbc6f2698 Merge "disp: msm: sde: flush commit thread queue during pm suspend" 2021-06-01 20:21:34 -07:00
Andhavarapu Karthik
5df7014990 disp: msm: sde: update perf cpu dma latency votes on idle in video mode
In video mode for fps greater than 60, perf cpu dma latency votes
are not removed during idle fallback. Made changes to remove and
add the perf cpu dma latency votes during idle fallback and idle
exit scenarios respectively.

Change-Id: I8dffc743bd48c96a6022935f71057a0223d9696e
Signed-off-by: Andhavarapu Karthik <kartkart@codeaurora.org>
2021-06-01 17:19:16 -07:00
Dhaval Patel
cfa81fdcaf disp: msm: sde: fix uidle disable configuration
Fix uidle disable setting when panel fps is beyond supported
FAL1 and FAL10 limit.

Change-Id: If76f1789f5f2677e503375234e8d4029c455d455
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2021-05-27 12:27:03 -07:00
Samantha Tran
f5a91ba3b3 disp: msm: sde: pass disp info to setup vsync source
While setting up vsync source, display info is used to decide whether
or not watchdog TE should be used. This change passes display info
as a parameter to vsync setup rather than using the encoder's display
info which is not updated in the case of panel dead error.

Change-Id: I928ee2012eec7bf63f4ba3538082bc3e47d5e99d
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2021-05-24 16:24:39 -07:00
Yashwanth
7e03fb61fd disp: msm: add support for seamless dsc switch
This change adds logic to determine dsc switch based on
the connector property "CONNECTOR_PROP_DSC_MODE" and
performs seamless DSC switch if there is any change in
DSC configuration. The connector property is populated
in msm_sub_mode based on which suitable mode is selected.

Change-Id: Ifc4931f16dfb814781bc1d72b103e09103e6bfee
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2021-05-20 21:34:27 -07:00
Yashwanth
ffc7cdbe08 disp: msm: add connector state along with crtc state to detect modeset
During modeset, private mode changed is detected from
msm_display_mode which is present in sde_connector_state.
In the current code, sde_connector_state is found from the
drm_connector variable which will not be valid
during atomic check phase and new connector state is
required here. To handle this, drm_connector_state is passed
along with the drm_crtc_state while detecting
msm_atomic_needs_modeset condition.

Change-Id: I62c162eff6e1c091cb05b3f049a40a0f25b710ba
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2021-05-21 03:48:21 +05:30
Samantha Tran
db1461c64b disp: msm: sde: disable RSC solver mode during HFR cases
During high framerate cases, disable RSC solver mode as there
will not be much power saving to be done. Disabling is decided
through panel timing node property.

Change-Id: I178170a5ab1b7e31b92ae3019e0147c05a282850
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2021-05-20 12:24:58 -07:00
Yashwanth
75f3403326 disp: msm: sde: add kickoff_in_progress flag in sde crtc
In dual display usecases, during pm suspend/resume,
commit is scheduled only on primary crtc thread. If idle
timeout value is very short such as in LP2 mode, it might
result in race condition due to idle pc off work getting
scheduled on its crtc thread. This change adds kickoff in
progress flag to handle such cases as crtc frame pending
count is only updated after rc kickoff.

Change-Id: Iebb331d914b23cc5eeadfeb2a488891e88b3202a
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2021-05-19 16:35:40 -04:00
qctecmdr
ff27df4031 Merge "disp: msm: sde: avoid reset topology in disable path for POMS" 2021-05-16 08:49:12 -07:00
Samantha Tran
ba95cccfec disp: msm: sde: avoid idle pc during ESD recovery
This change prevents entering into idle pc during ESD
recovery. In the event of a panel dead scenario, the panel
TE is no longer valid until display is enabled again. Until
the time display is enabled, idle pc will be blocked so
that display does not fall into then exit idle pc and
attempt to set the vsync source to this invalid panel TE.

Change-Id: Ibdc71b803d50923832f08b238a96aa28854aaea0
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2021-05-13 13:43:42 -07:00
Lei Chen
918fc54fc7 disp: msm: sde: avoid reset topology in disable path for POMS
Panel operating mode switch will not change topology and it will
not trigger atomic_check for encoder to reconfigure topology.
So add this change to avoid reset topology when mode set is triggered
by POMS or non-seamless display mode switch.

Change-Id: If1afb30a97bf2695dd8849f025c20b5561fa4b82
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
2021-05-12 22:21:18 -07:00
Prabhanjan Kandula
7c5fde4c27 disp: msm: sde: update back to back atomic check polling
In case of back to back atomic check only commit with modeset
handling, enable client to retry same commit and increase
timeout value used in polling for clear of rsvp-next.

Change-Id: Ied7acfbf0fe1f68282cfc36cdadf2d6aec6db40a
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
2021-05-10 14:50:58 -07:00
Veera Sundaram Sankaran
506508e1cd disp: msm: sde: remove unused functions from sde code
Cleanup unused functions from all modules in sde driver.

Change-Id: Ia0e72ab9c281b4200a63ce35bf184e83fe1db5d2
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2021-05-09 11:41:54 -07:00
Prabhanjan Kandula
f4923f071d disp: msm: sde: defer reset of topology property in disable path
Resetting connector topology property in atomic check phase can cause
issues in concurrency scenario of idle-pc restore for encoder disable
commit. Defer resetting topology property for disable case until encoder
disable actually happens.

Change-Id: Ib53fb5e63df0ab6a332e981b182771b87ef77838
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
2021-04-27 16:06:28 -07:00
qctecmdr
b0ea2d882f Merge "disp: msm: sde: remove check to commit RM resourses" 2021-04-27 06:11:35 -07:00
Dhaval Patel
a698dbe5aa disp: msm: sde: fix autorefresh enable/disable sequence
SDE RSCC solver state and autorefresh enable concurrency
is not supported. This change moves the rscc solver state
to disable to avoid concurrency. It also resets the autorefresh
software structure state when encoder is disabled. This allows
autorefresh reconfiguration with next encoder enable.

Change-Id: Idb8c722c823d9f46d3cd03e1b046da69c8d88fc4
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2021-04-26 10:27:15 -07:00
Nilaan Gunabalachandran
c233dee598 disp: msm: sde: remove check to commit RM resourses
Commit bd234c1885 ("disp: msm: sde: avoid irq enable/disable
during modeset") adds a check before reserving RM resources as
part of modeset. Without this reserve, the resources are not
always allocated during modeset. This change removes the check
around the rm reserve to ensure resources are committed.

Change-Id: Icbb47ad781a04a0cd39c0190e9653eff470af7a0
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2021-04-20 12:22:59 -04:00
Nilaan Gunabalachandran
7c138e3f3c disp: msm: sde: null check for pp hw before encoder mode set
During encoder modeset, driver does not check for ping pong hw
before going through with mode set. This change updates the check
at the encoder mode set and adds a check at the encoder wait
for irq.

Change-Id: If27faa29ee29040808473e44994f42c36980a45e
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2021-04-19 13:49:28 -04:00
Steve Cohen
e5fa459062 disp: msm: restrict AVR_STEP based on panel requirement
Some panels require a fixed step rate for a particular mode.
This change allows DSI panels to specify a single supported
step rate for each nominal fps rate which SDE will enforce
during atomic check of AVR parameters.

Change-Id: I049415449bc88ccd396fced16d4534251eac3a06
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2021-04-04 18:45:40 -04:00
Steve Cohen
cf86c94f8e disp: msm: sde: add support for AVR_STEP feature
Add AVR step support so SW can trigger a late frame and instead
of immediately triggering, HW will perform the update at the
start of the next step interval. This allows for a fixed SW
vsync timeline to be maintained in userland, eliminating the
usual drift from the actual HW vsync caused by a late frame.

This change adds AVR_STEP support via a DRM property.

Change-Id: I4cf8a296989805f134c2165a3bed0b050bb09c96
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2021-04-04 18:40:57 -04:00
qctecmdr
ccf41a547c Merge "disp: msm: sde: avoid irq enable/disable during modeset" 2021-04-03 06:52:12 -07:00