disp: msm: sde: avoid irq enable/disable during modeset
Avoid irq enable/disable during modeset and trigger frame as posted start frame. This saves mode_set time and also avoids unbalanced vblank_irq in this usecase. Change-Id: I06958da5e52bc2aca0ddc60d2783615f80a839a4 Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org> Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Этот коммит содержится в:

коммит произвёл
Tatenda Chipeperekwa

родитель
75037208b6
Коммит
bd234c1885
@@ -100,13 +100,12 @@
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* @SDE_ENC_RC_EVENT_PRE_MODESET:
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* This event happens at NORMAL priority from a work item.
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* Event signals that there is a seamless mode switch is in prgoress. A
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* client needs to turn of only irq - leave clocks ON to reduce the mode
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* switch latency.
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* client needs to leave clocks ON to reduce the mode switch latency.
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* @SDE_ENC_RC_EVENT_POST_MODESET:
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* This event happens at NORMAL priority from a work item.
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* Event signals that seamless mode switch is complete and resources are
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* acquired. Clients wants to turn on the irq again and update the rsc
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* with new vtotal.
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* acquired. Clients wants to update the rsc with new vtotal and update
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* pm_qos vote.
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* @SDE_ENC_RC_EVENT_ENTER_IDLE:
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* This event happens at NORMAL priority from a work item.
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* Event signals that there were no frame updates for
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@@ -1898,19 +1897,6 @@ static int _sde_encoder_rc_pre_modeset(struct drm_encoder *drm_enc,
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sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
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}
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ret = sde_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE);
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if (ret && ret != -EWOULDBLOCK) {
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SDE_ERROR_ENC(sde_enc,
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"wait for commit done returned %d\n",
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ret);
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SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
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ret, SDE_EVTLOG_ERROR);
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ret = -EINVAL;
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goto end;
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}
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sde_encoder_irq_control(drm_enc, false);
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SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
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SDE_ENC_RC_STATE_MODESET, SDE_EVTLOG_FUNC_CASE5);
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@@ -1945,8 +1931,6 @@ static int _sde_encoder_rc_post_modeset(struct drm_encoder *drm_enc,
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goto end;
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}
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sde_encoder_irq_control(drm_enc, true);
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_sde_encoder_update_rsc_client(drm_enc, true);
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SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
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@@ -2396,13 +2380,19 @@ static void sde_encoder_virt_mode_set(struct drm_encoder *drm_enc,
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if (ret)
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return;
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/* reserve dynamic resources now, indicating non test-only */
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ret = sde_rm_reserve(&sde_kms->rm, drm_enc, drm_enc->crtc->state,
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conn->state, false);
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if (ret) {
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SDE_ERROR_ENC(sde_enc,
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if (drm_enc->crtc->state->active_changed ||
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!(msm_is_mode_seamless_dms(msm_mode) ||
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(msm_is_mode_seamless_dyn_clk(msm_mode) &&
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sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE)))) {
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/* reserve dynamic resources now, indicating non test-only */
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ret = sde_rm_reserve(&sde_kms->rm, drm_enc, drm_enc->crtc->state,
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conn->state, false);
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if (ret) {
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SDE_ERROR_ENC(sde_enc,
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"failed to reserve hw resources, %d\n", ret);
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return;
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return;
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}
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}
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/* assign the reserved HW blocks to this encoder */
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@@ -276,7 +276,6 @@ struct sde_encoder_irq {
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* @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes
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* @enable_state: Enable state tracking
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* @vblank_refcount: Reference count of vblank request
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* @vblank_cached_refcount: Reference count of vblank cached request
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* @wbirq_refcount: Reference count of wb irq request
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* @vsync_cnt: Vsync count for the physical encoder
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* @last_vsync_timestamp: store last vsync timestamp
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@@ -327,7 +326,6 @@ struct sde_encoder_phys {
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enum sde_enc_enable_state enable_state;
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struct mutex *vblank_ctl_lock;
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atomic_t vblank_refcount;
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atomic_t vblank_cached_refcount;
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atomic_t wbirq_refcount;
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atomic_t vsync_cnt;
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ktime_t last_vsync_timestamp;
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@@ -330,8 +330,6 @@ static void _sde_encoder_phys_cmd_setup_irq_hw_idx(
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{
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struct sde_encoder_irq *irq;
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struct sde_kms *sde_kms;
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int ret = 0;
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u32 vblank_refcount;
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if (!phys_enc->sde_kms || !phys_enc->hw_pp || !phys_enc->hw_ctl) {
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SDE_ERROR("invalid args %d %d %d\n", !phys_enc->sde_kms,
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@@ -346,39 +344,13 @@ static void _sde_encoder_phys_cmd_setup_irq_hw_idx(
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sde_kms = phys_enc->sde_kms;
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mutex_lock(phys_enc->vblank_ctl_lock);
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vblank_refcount = atomic_read(&phys_enc->vblank_refcount);
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if (vblank_refcount) {
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ret = sde_encoder_helper_unregister_irq(phys_enc,
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INTR_IDX_RDPTR);
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if (ret)
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SDE_ERROR(
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"control vblank irq registration error %d\n",
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ret);
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if (vblank_refcount > 1)
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SDE_ERROR(
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"vblank_refcount mismatch detected, try to reset %d\n",
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atomic_read(&phys_enc->vblank_refcount));
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else
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atomic_set(&phys_enc->vblank_cached_refcount, 1);
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SDE_EVT32(DRMID(phys_enc->parent),
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phys_enc->hw_pp->idx - PINGPONG_0, vblank_refcount,
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atomic_read(&phys_enc->vblank_cached_refcount));
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}
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atomic_set(&phys_enc->vblank_refcount, 0);
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mutex_unlock(phys_enc->vblank_ctl_lock);
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irq = &phys_enc->irq[INTR_IDX_CTL_START];
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irq->hw_idx = phys_enc->hw_ctl->idx;
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irq->irq_idx = -EINVAL;
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irq = &phys_enc->irq[INTR_IDX_PINGPONG];
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irq->hw_idx = phys_enc->hw_pp->idx;
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irq->irq_idx = -EINVAL;
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irq = &phys_enc->irq[INTR_IDX_RDPTR];
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irq->irq_idx = -EINVAL;
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if (phys_enc->has_intf_te)
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irq->hw_idx = phys_enc->hw_intf->idx;
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else
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@@ -386,17 +358,14 @@ static void _sde_encoder_phys_cmd_setup_irq_hw_idx(
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irq = &phys_enc->irq[INTR_IDX_UNDERRUN];
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irq->hw_idx = phys_enc->intf_idx;
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irq->irq_idx = -EINVAL;
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irq = &phys_enc->irq[INTR_IDX_AUTOREFRESH_DONE];
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irq->irq_idx = -EINVAL;
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if (phys_enc->has_intf_te)
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irq->hw_idx = phys_enc->hw_intf->idx;
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else
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irq->hw_idx = phys_enc->hw_pp->idx;
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irq = &phys_enc->irq[INTR_IDX_WRPTR];
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irq->irq_idx = -EINVAL;
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if (phys_enc->has_intf_te)
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irq->hw_idx = phys_enc->hw_intf->idx;
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else
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@@ -821,7 +790,7 @@ static int sde_encoder_phys_cmd_control_vblank_irq(
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struct sde_encoder_phys_cmd *cmd_enc =
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to_sde_encoder_phys_cmd(phys_enc);
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int ret = 0;
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u32 refcount, cached_refcount;
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u32 refcount;
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struct sde_kms *sde_kms;
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if (!phys_enc || !phys_enc->hw_pp) {
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@@ -836,17 +805,11 @@ static int sde_encoder_phys_cmd_control_vblank_irq(
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goto end;
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refcount = atomic_read(&phys_enc->vblank_refcount);
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cached_refcount = atomic_read(&phys_enc->vblank_cached_refcount);
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/* protect against negative */
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if (!enable && refcount == 0) {
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if (cached_refcount == 1) {
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atomic_set(&phys_enc->vblank_cached_refcount, 0);
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goto end;
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} else {
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ret = -EINVAL;
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goto end;
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}
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ret = -EINVAL;
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goto end;
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}
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SDE_DEBUG_CMDENC(cmd_enc, "[%pS] enable=%d/%d\n",
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@@ -866,11 +829,6 @@ static int sde_encoder_phys_cmd_control_vblank_irq(
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atomic_inc_return(&phys_enc->vblank_refcount);
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}
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if (enable && cached_refcount) {
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atomic_inc(&phys_enc->vblank_refcount);
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atomic_set(&phys_enc->vblank_cached_refcount, 0);
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}
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end:
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mutex_unlock(phys_enc->vblank_ctl_lock);
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if (ret) {
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@@ -2108,7 +2066,6 @@ struct sde_encoder_phys *sde_encoder_phys_cmd_init(
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irq->cb.func = sde_encoder_phys_cmd_wr_ptr_irq;
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atomic_set(&phys_enc->vblank_refcount, 0);
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atomic_set(&phys_enc->vblank_cached_refcount, 0);
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atomic_set(&phys_enc->pending_kickoff_cnt, 0);
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atomic_set(&phys_enc->pending_retire_fence_cnt, 0);
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atomic_set(&cmd_enc->pending_vblank_cnt, 0);
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