Commit Graph

718 Commits

Author SHA1 Message Date
qctecmdr
e5e4004854 Merge "disp: msm: sde: avoid physical encoder disable(s) in trusted VM" 2020-06-28 01:57:54 -07:00
qctecmdr
1b5e5c1590 Merge "disp: msm: specify default value for msm enum property" 2020-06-27 23:15:27 -07:00
Linux Build Service Account
8fb0e26527 Merge "disp: msm: sde: add xin client clock status for wb2" into display-kernel.lnx.5.4 2020-06-26 18:53:49 -07:00
Samantha Tran
d46c9286e5 disp: msm: sde: update uidle wd timer load value and fal1 threshold
Update the uidle wd timer load value to 18. This change will allow
a 15us wd timer per hardware recommendation.

Update fal1 threshold value to take the minimum of 15 or the
current setting which takes line time and target idle time into
consideration. The target idle time is also being updated from 10us to
40us.

Change-Id: Ia8d9c2070813beef18fdf342526d82cf8f82989b
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2020-06-26 13:54:33 -07:00
Prabhanjan Kandula
690139ccd1 disp: msm: sde: serialize rm reserve for check only commit
During back to back mode set, current driver logic fails
atomic check during resource allocation with test only if
previous commit also with modeset, has tagged resources for
allocation but did not commit the resources yet. Since client
invoking atomic check before previous mode set commit complete
is an expected scenario now, instead of failing atomic check,
this change allows resource allocation for next commit also go
through by pollong till the first mode set is complete.

Change-Id: I1261b7d205bb0d886085664fab3664162a419c99
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
2020-06-26 10:38:43 -07:00
Dhaval Patel
44cde01fc7 disp: msm: sde: manage vblank refcount concurrency
Vblank refcount can reach out of sync with below case
 1. event_thread triggers the vblank_enable
 2. commit_thread triggers the modeset
   2.a modeset resets the vblank refcount with mode_set
 3. event_thread triggers the vblank_disable

Event 2.a resets the vblank refcount and vblank disable
request after 2.a is going to fail. This can be fixed
by avoiding concurrency between mode_set call and vblank
request.

Change-Id: Ibb810ec90e81d63feee443f1c37dd736d5cfac0d
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2020-06-25 13:54:21 -07:00
Veera Sundaram Sankaran
88037da799 disp: msm: fix vram allocation when IOMMU is not present
Allocate DSI/LUTDMA buffers from VRAM when IOMMU is not
available. Add checks in msm_gem to avoid few operations
when aspace is not available due to no IOMMU. Parse the
VRAM size from device tree, when available.

Change-Id: Iedf5749b71c2e772ac5434048520a34705c54b45
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2020-06-24 16:20:38 -07:00
Amine Najahi
8479ed7278 disp: msm: sde: dump clock state before entering suspend
Add debug capability to dump clocks before entering pm suspend.
This will help debug invalid register access when clocks are off
during adversarial test cases.

Change-Id: I80d19b751a3b9a1de0cc64699a21a1852d614ced
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
2020-06-22 13:40:03 -07:00
Jeykumar Sankaran
8b032e5e46 disp: sde: add CRTC property for VM requests
Add a CRTC property to request the VM to acquire/release
HW resources.

Display driver in trusted VM boots up without HW ownership. Set
the default value of the property as RELEASED to handle resource
assignments.

Change-Id: Iea651a2fea902d95d4b954052af4ef016af15a91
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
2020-06-19 17:46:43 -07:00
Jeykumar Sankaran
06ab29478d disp: msm: sde: avoid physical encoder disable(s) in trusted VM
VM switches during TUI usecase are expected to be seamless i.e without
display reset. In SDE language, this translates to respective display
drivers not tearing down the HW pipeline while releasing the HW.

In Primary VM, this taken care by keeping the DRM pipeline alive when
TUI is active.

In Trusted VM, since the client creates and destroys the display per
session, checks are needed to bypass the physical encoder disable(s).

Change-Id: Iac42f02806962405c9364b1ffed85778229977e9
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
2020-06-19 17:46:43 -07:00
Jeykumar Sankaran
98a6a1131c disp: msm: sde: add capability flag for trusted VM support
Add a new hw catalog flag to indicate target support for
trusted VM. Currently, the flags is set for Lahaina target.

Change-Id: Idb56492758ef580673b2ebf44fecd577a2876f1b
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
2020-06-19 17:46:43 -07:00
Prabhanjan Kandula
f946219084 disp: msm: sde: update sspp multi rect programming
Current SDE driver allows staging of rect1 only configuration. When a
real plane is disabled sspp multi rect configuration is not updated.
This can lead to iommu faults and ping pong timeouts as framebuffer of
disabled plane is unmapped. This change fixes it by updating multi rect
config accordingly when a plane is disabled.

Change-Id: I67ae45ad0e607184c7fc49f4b220220ba1d8a2ae
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
2020-06-19 16:45:29 -07:00
Dhaval Patel
31d4bb10a6 disp: msm: sde: add xin client clock status for wb2
CWB may trigger frame missed message if interrupts
are disabled on specific CPU. WB2 will only find single
interrupt status for two posted start triggered frame.
SDE driver will start checking the xin client clock
status for wb2 timeout case to trigger the valid
frame done status.

Change-Id: I16a99667116732002e6dec8a18330f8b45199387
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2020-06-19 16:28:14 -07:00
Jeykumar Sankaran
935af8104a disp: msm: sde: avoid MDSS register access during boot in trusted VM
Trusted VM will be assigned MDSS HW access dynamically only on TUI
use case start boundary. So, any HW access during the boot sequence
will result in stage2 faults. But SDE driver initializes few HW
blocks during the boot up sequence. This change fixes them by either
skipping those accesses, if those registers expected to be programmed
by the Primary VM or postponing those accesses until the HW is
assigned.

Change-Id: Ic85238c5d734e9ac993072374c1b0ae661708fca
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
2020-06-19 15:39:03 -07:00
qctecmdr
743dc695c4 Merge "disp: msm: sde: fix cwb enable detection logic" 2020-06-19 12:44:59 -07:00
Veera Sundaram Sankaran
bd28c729e8 disp: msm: refactor dma buf attach device assignment
Assign default drm device for dma buf_attach when
IOMMMU is not present and for stage-2 only buffers.
Avoid setting lazy_unmap for stage-2 only buffers as
it doesn't have any impact without nested translations.
Assign default drm device when no device is found to
support transitions between secure usecases where
the nested context banks might not be attached back
at the prime_fd_to_handle time. These buffers would
be attached with the correct context bank device
during the delayed_import.

Change-Id: I9ccb38876d7843b4411762c7b8006ae8fca85391
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2020-06-19 11:36:29 -07:00
qctecmdr
1bd126d328 Merge "disp: msm: sde: add dt property for QSEED scalar HW revision" 2020-06-19 02:38:54 -07:00
Jeykumar Sankaran
cb4f390241 disp: msm: sde: add helper api to check executing VM
Adds a DT property to indicate trusted VM execution
environment and support catalog parsing for the same.
Add helper API to read the value.

Change-Id: I9194618b6f080119f1f15271a9b3c7edf938ca08
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
2020-06-18 11:28:40 -07:00
Dhaval Patel
1eda6392b0 disp: msm: sde: fix cwb enable detection logic
Existing cwb enable detection logic relies on
crtc id matching with each encoder->crtc. This
may not be available on first power on commit
because it updated after encoder_atomic_check
call. This patch fixes the cwb enable detection
logic by checking the encoder_mask on crtc_state.

It also fixes the cwb concurrency with mode_set
and secure display.

Change-Id: I70f656dd9e7d94d3ba761c25745b473a1c204173
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2020-06-17 16:49:16 -07:00
Jeykumar Sankaran
b87b13690b disp: msm: specify default value for msm enum property
Allow caller to specify the default value of the enum
property while installing with msm prop layer. It is
not always the case that the default value to be the
first entry.

Change-Id: Ie0bb1ad7479e3e07810b3d817fdf618b1935858c
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
2020-06-17 15:36:33 -07:00
Ram Chandrasekar
53654b534a disp: msm: sde: Register display brightness cooling device
Register for getting a blocking notified call when the display cooling
device mitigates. Update the current brightness to the thermally allowed
level.

Change-Id: I20945a20751646e6d9bbf8bb7e7039c6ce43c306
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
2020-06-16 13:45:39 -07:00
Lakshmi Narayana Kalavala
a27534e143 disp: msm: sde: Add checksum support for LTM for lahaina target
This change adds the support for checksum collection and notifies
to user space as part of drm event.

Change-Id: Ib2a6c38c74d1fb60d274cdb685b74979202604eb
Signed-off-by: Lakshmi Narayana Kalavala <lkalaval@codeaurora.org>
2020-06-15 20:13:14 -07:00
qctecmdr
4b24ccb9d8 Merge "disp: msm: sde: avoid access out of range issues in sde cp code" 2020-06-12 22:59:38 -07:00
qctecmdr
654eed0a06 Merge "disp: msm: sde: allow frame_done count to reach till 2" 2020-06-12 22:59:38 -07:00
Jeykumar Sankaran
fdf88f7853 disp: msm: sde: add dt property for QSEED scalar HW revision
QSEED scalar block HW revision is constant for a given MDSS revision.
Both SSPP and DS HW files invoke this API to read the revision register
at various points of time. Expose this revision information through
DT binding and maintain in the catalog to avoid repeated register
reads.

Change-Id: I95c0a5242cfda0aaa4ec5c2ff5c7cc0bed191b59
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
2020-06-12 14:29:42 -07:00
Jeykumar Sankaran
7f35be34eb disp: msm: sde: rename qseed_type to qseed_sw_lib_rev
Rename the property to qseed_sw_lib_rev to indicate that it
represents the qseed sw library revision that is compatible with
the targets qseed hw version.

Change-Id: I5a588dc20cf4a4f76f5c71301538bfc630ea220d
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
2020-06-12 14:29:25 -07:00
qctecmdr
b61dbb8b6c Merge "disp: msm: sde: make all HW definitions unsigned" 2020-06-12 08:04:21 -07:00
qctecmdr
68a42554a1 Merge "disp: msm: sde: remove pipe fetch halt check on real plane" 2020-06-12 03:53:37 -07:00
qctecmdr
d9b4204aad Merge "disp: msm: sde: add vig formats before qseed and csc initializations" 2020-06-12 00:11:19 -07:00
qctecmdr
88abc2fad2 Merge "msm: sde: Uprev IGC version to 4.0 to indicate existence of LUT 257" 2020-06-11 20:34:33 -07:00
Dhaval Patel
bbcb96a8e5 disp: msm: sde: allow frame_done count to reach till 2
A frame trigger with posted start may have two frames
in wait state due to irq disable on that CPU. In such
case, frame_done count can reach till 2. Allowing count
only till 1, can cause the release_fence trigger miss
and a buffer is held by DPU driver.

Change-Id: I42c10b064ebcaff136591975f3010c11f99a0731
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2020-06-11 17:28:01 -07:00
Nilaan Gunabalachandran
ebc016b6e4 disp: msm: sde: make all HW definitions unsigned
Treating hw version as a signed int results in a negative
number when major version is more than 7, leading to errors
when comparing versions in the driver. Fix this by making
sure all HW version definitions and variables are unsigned.

Change-Id: Ic77183f85e5408092e05817cf95df5b0f0fcac75
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2020-06-11 08:36:05 -04:00
Dhaval Patel
5d8bfac54d disp: msm: sde: remove pipe fetch halt check on real plane
SDE driver started supporting multirect mode with rect_1 only
configuration. In such case, master plane can not trigger
pipe fetch halt independently. This change removes the pipe
fetch halt check completely because it was only done for
master plane without buffer flip usecase. AXI fetch halt
provides similar functionality during idle power collapse
and suspend-resume.

Change-Id: I79d9d0eac2de95f1bb88561c7cc259e0cc4b2ca4
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2020-06-10 18:23:11 -07:00
qctecmdr
621a624d8c Merge "disp: msm: fix kw issues in sde driver" 2020-06-10 17:06:50 -07:00
Christopher Braga
a17846fecd disp: msm: sde: avoid access out of range issues in sde cp code
Address out of range issues due to faulty and missing
array size checks.

Change-Id: I2aefb1b8d4015a73ea87a64182e090247f5a9da0
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
2020-06-10 15:10:41 -07:00
qctecmdr
8975496690 Merge "disp: msm: sde: adjust DSC encoders to support all 4LM topologies" 2020-06-09 23:42:41 -07:00
Christopher Braga
394f727493 msm: sde: Uprev IGC version to 4.0 to indicate existence of LUT 257
Change IGC version to 4.0 to clearly indicate that support
for LUT 257 in DSPP is now supported and expected.

Change-Id: Ie3bb5b0150bdf6c332f86d0ae416b4f6fc42e70f
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
2020-06-09 18:41:48 -07:00
Amine Najahi
ed868466f5 disp: msm: dp: Extend mode filtering to support 8K
Currently DP driver determines if a mode is DSC capable
based on a DTSI entry and the required number of DSC
to support it. This approach does not scale when there
is an overlap in DSC requirement between DSI displays
and external DP display, thus causing one of the display to
report modes that cannot be supported.

This change compares the resources reserved for DP driver
calculated at initialization time and the currently available
ones to determine the correct number of resources that DP driver
can use. It also adds DSC and topology filtering logic and moves
DSC hardware specific from DP driver to SDE driver.

Change-Id: I8e601de33422b7c6d786826f7bfe152c4af8a6b5
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
2020-06-09 09:17:38 -04:00
santosh
fb72c8faa8 disp: msm: sde: add vig formats before qseed and csc initializations
Setup vig pipe makes an early return if csc and qseed are
not supported. This change moves addition of vig formats
before intializing qseed and csc.

Change-Id: I2eb651f7bbd81757a9de23501fda51a510d0e673
Signed-off-by: santosh <santoshkumar@codeaurora.org>
2020-06-08 11:40:05 -07:00
Jayaprakash
19253d6e19 disp: msm: sde: modify the args for sid switch call
Modify the size of SID's passed as an argument during
scm call as per client requirement.

Change-Id: Idd3bb57a8f9e0a4e7eb6a23d96bfa5b68510063a
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
2020-06-08 11:39:59 -07:00
Krishna Manikandan
74f3b5a9de disp: msm: sde: allow kthread init for off work during cwb
During transition to cwb, kthread initialisation has to
be done for the corresponding encoder off work so that
the correct worker thread is used for this particular
work. There can be scenarios where a cwb commit is
received after a writeback session and the worker
associated with the off work is still assigned to
old crtc's worker resulting in a mismatch when
this work is queued. Add support to handle such
scenarios.

Change-Id: I6080025e799977827f4d0f4ab7eb93c6644f981e
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
2020-06-08 11:39:48 -07:00
Raviteja Tamatam
889c4786ae disp: msm: sde: enable dim layer setup event log
Enable dim layer event log to know the composition of all
blend stages in a commit from xlogs.

Change-Id: I387fd888f06f0c61d2042896459119d614b3f60b
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
2020-06-08 11:39:43 -07:00
Yashwanth
5792eb97d1 disp: msm: sde: add check for max encoder limit during allocation
This change checks max limit while allocating encoders
during display init.

Change-Id: I48736667c2b83f916f09f9e81cb1b24a9fef215a
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2020-06-08 11:39:36 -07:00
Yashwanth
45e57a9f87 disp: msm: sde: add ubwc verification during plane atomic check
In targets where ubwc is not supported, atomic check
should fail and return a error value if the input format
is ubwc.

Change-Id: I21a40f510cc852e64fbcc05a5fb4848da4b4faaa
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2020-06-08 11:39:31 -07:00
Jayaprakash
11aab5f9c3 disp: msm: sde: Fix null dereference errors
Add changes to avoid NULL dereference access and
uninitalized access in sde driver.

Change-Id: Ic9c06f54d1ccd820973fc0ba4aa75d2848f2ce03
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
2020-06-08 11:39:25 -07:00
Ray Zhang
3bfb8cafce disp: msm: support framebuffer emulation in KMS driver
framebuffer support is required in some use cases, so add
framebuffer emulation for KMS driver.

Change-Id: Icf0bbcd59ca430478d2bef4df033988d0338f2bb
Signed-off-by: Ray Zhang <rayz@codeaurora.org>
2020-06-08 11:39:17 -07:00
Yashwanth
4194c7b7cd disp: msm: sde: add dt based support for pm qos irq latency
This change adds dt based support for pm qos irq
latency instead of using hardcoded value.

Change-Id: I9f67ed1092eefac193a409773f841350532bc722
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2020-06-08 11:39:09 -07:00
Jayaprakash
bada02f317 disp: msm: sde: add changes to fix get connector failure in rm_release
Currently during rm_release, drm_conn is available only if connector
and encoder are bound together. If a test_only commit occurs
before a non-blocking modeset commit, this bound is uncertain.
The resources allocated by test_only commit will not be released
and leads to resource allocation failures for the consequent
commits. Add changes to modify this by checking for the encoder
attached to sde_connector which happens during bootup.

Change-Id: Icb1d9595efda8a104ba527175b2dbc6a2c856d44
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
2020-06-08 11:39:03 -07:00
Dhaval Patel
83860f0642 disp: msm: pass free dsc and lm availability info to dp
Primary and secondary dsi displays are built-in displays
and they are supported during all concurrency usecases
without resource allocation failure. DP mode filter
logic should provide supported mode information based
on free mdp resources after dsi resource assignment.

Change-Id: I3a9637a91ea1ffcc31997e25caff7f13605283ac
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2020-06-07 22:57:26 -07:00
qctecmdr
fae3dc03b4 Merge "disp: msm: sde: fix system cache feature enable" 2020-06-05 13:33:28 -07:00