This change enables support for wb1 in ctl path and
adds irq support.
Change-Id: Iebbe35725aa279b8e02217ea93ba1b481f5e869f
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
Add kalama mdss revision and enable features based
on the hardware capability.
Change-Id: I27dff07b00ba16d313c5c8dc2661a10e522daea5
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
The sde_hw_blk was meant to be a generic base object for all
SDE HW blocks, however, it enforces using a common set of ops
which is not practical when blocks have different capabilities.
Since this object was never used as intended and is not doing
anything functional today, remove the dead weight.
Change-Id: If76006c1ae5c62e8d7d77b100837dbaf6c661bd3
Signed-off-by: Steve Cohen <quic_cohens@quicinc.com>
Many upstream files and APIs have been removed in downstream
driver. Some function definintions are left dangling without
any caller. Remove the functions which are not used downstream.
Change-Id: I9f936e7cdac3be6f854b3c67725164fad785f0d4
Signed-off-by: Steve Cohen <quic_cohens@quicinc.com>
Align the HW catalog to use common naming amongst the "revision"
and "version" structure members.
Change-Id: Ib6c81aee6cb49208b0699db4a75b4eb9dc79e800
Signed-off-by: Steve Cohen <quic_cohens@quicinc.com>
Move all the individual boolean flags from HW catalog into a
"features" bitmap. These flags are used to specify support of
various target specific features.
Change-Id: I2334b3b873f3737f91bbae4ef576408247710156
Signed-off-by: Steve Cohen <quic_cohens@quicinc.com>
Add const qualifier for the device_node param in get_named_gpio
function pointer hook to adapt msm-5.15 kernel.
Change-Id: I0129efeff5aeb85b567bf6f2b5d2e45312fab024
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Remove memblock_free api, since currently is not
part of the ack tree. This prevents modpost compilation
errors for the display driver.
Change-Id: I8f657a123fbecc5d4b029d511b8d08fec2293f0c
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
Latest Kernel modified list_sort to receive 'const' parameters in
its function pointer, this change modifies the functions used
by list_sort to add 'const' parameters.
Change-Id: I83212e1e7a749132c90011d0a8933c5eb2990bd2
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
Update the msm layer to use linux IRQ interfaces as DRM IRQ helpers
are removed in 5.15 kernel.
Change-Id: I9f41032927cddabe8a5a48e5e9339acef6c6f67e
Signed-off-by: Bruce Hoo <bingchua@codeaurora.org>
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Update msm_gem and msm_drv to comply with latest 5.15 kernel.
Modify dma_buf_vmap() and dma-buf's vmap callback to use
struct dma_buf_map. Rename dma_resv_get_excl_rcu to _unlocked.
Remove deprecated GEM and PRIME callbacks.
Change-Id: Ifdfc7f872c988d8455f465e7d17dfbcf212bb5f6
Signed-off-by: Bruce Hoo <bingchua@codeaurora.org>
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Pass additional parameters to supply maximum lane count and
rate to MST topology manager. In cases where sources have
lower maximum lane count or rate than default MAX_LINK_RATE,
these values will be used instead.
Change-Id: I9278ce6cc9fbacaf3f6d964c5036208c0695a79b
Signed-off-by: Bruce Hoo <bingchua@codeaurora.org>
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
This change moves the point at which msm_gem_object is added to
inactive list. Moving this ensures that initialization will be
complete before adding the object to the list. This change also
removes unused functions from msm_gem.c.
Change-Id: Id8fa04cc88a21e04108ae21b18d5acc761ef4c6e
Signed-off-by: Bruce Hoo <bingchua@codeaurora.org>
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Update names of DSI flags to follow upstream convention. Purpose of
the name change is to more clearly indicate what is not supported
when the flag is set.
Change-Id: Ifd62610c4dfebcbbccb0fb2046a7c453e39c9107
Signed-off-by: Bruce Hoo <bingchua@codeaurora.org>
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Pass full state to crtc, plane, and connector atomic functions and retrieve
drm_crtc/plane/connector_state within the atomic function. Additionally,
the plane atomic update function is used as an upstream hook as well as
locally called in the plane restore path. To ensure both paths are functional,
introduce a plane atomic update version which takes in drm_plane_state
keeping with the previous parameter expectations.
Change-Id: Ia295935dd81ea8680a347eba0929e209d93ae830
Signed-off-by: Bruce Hoo <bingchua@codeaurora.org>
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Pass additional parameter drm_dp_aux to drm_dp_link_train APIs
in order to use drm_dbg_* within those functions.
Change-Id: Icc111ecce78fbbac77eb044ce4200377d3616fc9
Signed-off-by: Bruce Hoo <bingchua@codeaurora.org>
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Include of_common header file explicitly to use
of_fdt_get_ddrtype().
Change-Id: Idd814d6188d585b2d0ecd6935f3260a79d15401b
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
API got deprecated in kernel 5.15. Remove the usage.
Change-Id: I10c4fdee1074fcf50ae4fe28124692dae7a31c7c
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
After adapting dma buf api's these references and
paths are unusable. Clean it up.
Change-Id: Id6fa76945132e312e8bacf6e430633b0db9e48a3
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Domain attributes has been deprecated on 5.14 kernel, so replace
msm_smmu_set_attribute with qcom_iommu_enable_s1_translations.
Change-Id: I1bf2d5ee089a418eb73605327e82b2e26bd6bada
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Commit b67da33a6307 ("trigger tx_wait if panel
resolution switch") increases the mode switch latency.
Alternatively, single buffer tear check registers can be
updated when vsync_in is disabled. It allows mode switch
frame trigger as posted start frame trigger.
Change-Id: I8068736b2ea01f6e4160e765fc39d7fc2a8590c9
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
* waipio_base:
disp: msm: sde: add new support for digital dimming
disp: msm: sde: trigger tx_wait if panel resolution switch
disp: msm: reserve core clock rate during display disable
disp: msm: dsi: reorder DSI registration
disp: msm: sde: account for pref lm when exposing avail resources
disp: msm: reset lm blend stages for missing vsync
disp: msm: dp: set drm mode clock same as clock value from EDID
disp: msm: sde: set top left coordinates for noise and attenuation layers
disp: msm: dp: disable ASSR before link training
disp: msm: dp: retry the request to set USB mode during bootup
disp: msm: sde: clear intf mux select on slave encoders
disp: msm: retry dma buf attach on msm_gem_delayed_import error
disp: msm: dp: check for aux abort in sim mode
disp: msm: dsi: add qsync min fps val in dsi display mode priv info
disp: msm: dp: read DPCD registers using debugfs
disp: msm: dsi: mark signature for stub appropriately
disp: msm: dp: check for DP stream during audio teardown
display: msm: sde: reduce dbg mem usage for tui vm
Change-Id: I285e4557ad258f17fc2948b478198b9b81c18276
Wait for asynchronous DSI DCS command transfers to complete
before disabling DSI interrupts during pre-release. This is
required to resolve a race condition where dsi worker threads
can trigger HW access while a VM lend/release is occurring on
the CRTC commit thread.
Change-Id: Ia1f153a2cd008c617dba274473e7678b01a38d29
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
The ROI commands are sent with an asynchronous command transfer wait.
If the queued CMD DMA wait for done gets scheduled before the DSI
controller timing engine programming, the later will be blocked waiting
on the ctrl_lock, which was acquired by the queued DMA wait for done work.
This effectively negates any advantage of having the async wait flag for
ROI commands blocking the main commit thread.
The change swaps this order to ensure that such a scenario never happens.
Change-Id: I8a971c0c7733eea3d435b637ca41b34fa60adfc1
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
During display encoder disable, reset the dsc control
mux configuration during null commit to ensure dsc hw
blocks are cleanly freed up.
Change-Id: I02e2f074450e4d7b49dc8fec14777f380786c63e
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
While hw resources allocation for an active display during modeset, avoid
dsc hw allocation switch by finding which dsc encoders are allocated
previously and allocate same dsc hw encoders. This helps in fixing underrun
issues in below scenario of dual display power ON/OFF.
Use case: Dual DSI display setup, both are DSC enabled, primary in video mode.
--> when both displays are in powered off, all hw block are free.
--> enable second dsi display
Since LM 0/1 marked for primary, LM 2/3 allocated along with DSC 0/1
--> enable primary display
LM 0/1 allocated with DSC 2/3 encoders
--> Now power off secondary DSI
DSC 0/1 are freed up
--> Immediate modeset on primary, DSC allocation switched
LM 0/1 and DSC 0/1 allocated. DSC 2/3 are freed up as per RM but
decoupling DSC 2/3 blocks with respective pingpong or intf is not done.
This is causing underruns on primary.
Tracking which DSC blocks are freed during resource switch and programming the
respective DSC control mux configuration is not feasible and not scalable as
any other display can allocate those blocks and would require synchronizing
across display threads. So approach taken is avoid dsc resource switch itself.
Change-Id: I7f740722a52266740c4b168edc0c619e3cf68989
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
Adjust pll pclk rate to support non 1/1 dispcc MND
divider values by updating pclk div calculation.
Change-Id: I1972b536a109b97978e843f046b1db4ad6813a51
Signed-off-by: Srihitha Tangudu <tangudu@codeaurora.org>
Add new properties to support dynamically turning on and off digital
dimming and setting new minimum backlight.
Change-Id: I3b94190877d556768ba2c92ec59432dec44de0de
Signed-off-by: Ping Li <pingli@codeaurora.org>
Trigger tx_wait if command mode panel resolution
switches during mode switch to avoid early single buffer
tear check programming.
Change-Id: Ib747df8250c714248a44b596c2c8aeef006ea4fc
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Userspace module may not trigger the atomic check and it
can cause the commit failure. In such case, always reserve
the minimum core clock rate on mmrm module for built-in
displays to avoid the power ON failure.
Change-Id: Iafd92a7b7d1b35befe70b041cbedaec2add40de4
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Reorder registration of various display drivers in the order of
dependency.
Change-Id: Idfa0616d3133f3b03c713e3c15a4fd3956ec2594
Signed-off-by: Shashank Babu Chinta Venkata <sbchin@codeaurora.org>
If an external display, such as DP, requests for the available
resources, resource manager (RM) will provide a count of all unused
mixers. If the primary/secondary display(s) are not active, the RM
will report the associated preferred mixers as free resources.
However, RM will not allow preferred mixers to be allocated to other
displays. DP driver could look at these available resources and assume
a high resolution mode is possible and fail during resource allocation.
This change updates the available resources info API to account for
primary/secondary preferences while exposing available resources.
Change-Id: I134a1047f24ac9f1fcee695aa14a1d3e43c1571f
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
MDSS INTF HW block does not generate vsync if controller
turns off the link clock prematurely. This leads to
frame trigger timeout and SDE driver triggers the retire
fence after 84ms to recover gracefully. A client may switch
source pipe from one CTL path to another CTL path based
on delayed retire fence. It can lead to other ctl path
hang. This can be resolved by resetting the lm blend
stages for each missing vsync frame trigger.
Change-Id: I5a6ed03afbdad83d8fd6decc593d39e04bef62e4
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Commit Ie972a2e140adfd81c4e68df8e7bc69feaaca22e1 updated the dp
driver to extract the drm mode clock from timing parameters
instead of using the clock value provided by EDID to align the
behavior with DSI driver. But this results in incorrect clock
value if the refresh rate is not an integer value. For rates
such as 59.94 or 29.97, the calculated mode clock value would
be different from what is stipulated by EDID. This change
reverts the mode clock calculation to use the clock value
from EDID.
Change-Id: I3e192ef09d2456fbb1d22a0bf9474ac25ba86c72
Signed-off-by: Sandeep Gangadharaiah <sandgang@codeaurora.org>
