Implement changes to make the driver compatible with bolero V2.2.
Change-Id: If2797a80f775c685ff2a6912de189b1d9b4906d0
Signed-off-by: Vangala, Amarnath <quic_avangala@quicinc.com>
When requested clk is not default clk, it should not enable
VA_MCLk directly. lpass_cdc_clk_rsc_check_and_update_va_clk
will take care of VA_MCLK switch.
Change-Id: I602be7dcc0228fd2e6ecd7624a96663e89485bd0
Signed-off-by: Meng Wang <mengw@codeaurora.org>
Because of a HW limitation in DSP, while switching
RCG from TX MCLK to VA MCLK for SVA use cases
a glitch is seen on AHB bus leading to data
corruption in registers.
So, while doing a mux switch for VA RCG clock selection,
do not configure the muxsel register in HLOS as it is
taken care in DSP itself as a workaround for HW limitation.
Change-Id: Ie36ff239689e634f5c29ad03b343b95de2d12547
Signed-off-by: Meng Wang <mengw@codeaurora.org>
Check if clk is enabled before disabling it to avoid
warning log during adsp SSR.
Change-Id: I916af6f9efacfe3d08e0b05dcc0c6023944369d2
Signed-off-by: Meng Wang <mengw@codeaurora.org>
Update the codec clock sequence as per the hardware recommendation
to enable the codec clockes on the latest codec version.
Change-Id: I1869d2b28c9aa79979f1aa3c85ca805cea3ef33b
Signed-off-by: Sudheer Papothi <spapothi@codeaurora.org>
Add driver support to enable lpass digital codec for
audio playback and capture usecases.
Change-Id: I3d31d31f340db79334700e8fd495f40479e0ec6c
Signed-off-by: Sudheer Papothi <spapothi@codeaurora.org>
