Implement hal_rx_mpdu_get_addr3 API
based on the chipset as
the macro to retrieve addr3 value is
chipset dependent.
Change-Id: I3983599b656e82170de5905c08daee3ec164e7a0
CRs-Fixed: 2522133
Implement hal_rx_mpdu_get_addr2 API
based on the chipset as
the macro to retrieve addr2 value is
chipset dependent.
Change-Id: I4026db892d4f2f41db72c50f780ba898b8a17fa7
CRs-Fixed: 2522133
Implement hal_rx_mpdu_get_addr1 API
based on the chipset as the macro to
retrieve addr1 value is
chipset dependent.
Change-Id: I7ed88f2243d397c9d605a08d3b93e17f0004c63d
CRs-Fixed: 2522133
Implement hal_rx_get_mpdu_frame_control_valid API
based on the chipset as the macro to retrieve
frame control valid value is chipset dependent.
Change-Id: I49d16ae44b2e9567ff746d2088058f0c1025ea40
CRs-Fixed: 2522133
Implement hal_rx_mpdu_get_fr_ds API
based on the chipset as the macro to
retrieve for_ds value is chipset
dependent.
Change-Id: I6d41d02ac50cae752567d98645f0447cc122a84f
CRs-Fixed: 2522133
Implement hal_rx_mpdu_get_to_ds API based
on the chipset as the macro to retrieve
to_ds bit value is chipset dependent.
Change-Id: I36d9d14e226bcc604b91d8aecbe52836c5a12272
CRs-Fixed: 2522133
Implement hal_rx_mpdu_start_sw_peer_id API
based on the chipset as the macro to retrieve
sw_peer_id value is chipset dependent.
Change-Id: Ifebaf2430731f5e0593dde4789d721e9fe7ce7c1
CRs-Fixed: 2522133
Implement hal_rx_get_mpdu_mac_ad4_valid API
based on the chipset as the macro to retrieve
mac_ad4 value is chipset dependent.
Change-Id: I9d7cc90e798d4f0775e915fe6edcb1a1f5129490
CRs-Fixed: 2522133
Implement hal_rx_msdu_end_last_msdu_get API
based on the chipset as the macro to retrieve
last_msdu value is chipset dependent.
Change-Id: I561c28a49062d7b650e68c5a4ce4da0183be34d6
CRs-Fixed: 2522133
Implement hal_rx_msdu_end_dat API based on
the chipset as the macro to retrieve da_is_valid
value is chipset dependent.
Change-Id: I79f06eaa2576e7516c21f963b2c149aac7f62c64
CRs-Fixed: 2522133
Implement hal_rx_msdu_end_first_msdu_get API
based on the chipset as the macro to retrieve
first_msdu value is chipset dependent.
Change-Id: Iea325159a0349c45a249c1ae113664c41a54b0f1
CRs-Fixed: 2522133
Implement hal_rx_print_pn API based on the
chipset as the macro to retrieve
pn value is chipset dependent.
Change-Id: Id9d0d3b34a5f6a09fe5903e1d24bb0a59205174b
CRs-Fixed: 2522133
Implement hal_rx_encryption_info API based
on the chipset as the macro to retrieve
sa_idx value is chipset dependent.
Change-Id: I0c48800dfa5628898c53f7a9271e517b6bfa3da7
CRs-Fixed: 2522133
Implement hal_rx_msdu_end_l3_hdr_padding_get API
based on the chipset as the macro to retrieve
sa_idx value is chipset dependent.
Change-Id: Ice1fc2d70e339dc1d80fa6f34f37c5a7aa074be5
CRs-Fixed: 2522133
Implement hal_rx_desc_is_first_msdu API
based on the chipset as the macro to
retrieve first_msdu bit value is chipset
dependent.
Change-Id: I8e8a3aceb225b591b96e6f8453ffbebf1f78e529
CRs-Fixed: 2522133
Implement hal_rx_msdu_end_sa_idx API
based on the chipset as the macro to
retrieve sa_idx value is chipset
dependent.
Change-Id: Ib874520be9e7ad778c2a9a3c415e5c3047450b31
CRs-Fixed: 2522133
Implement hal_rx_msdu_end_sa_is_valid_get API
based on the chipset as the macro to retrieve
sa_idx valid bit is chipset dependent.
Change-Id: I8bcb7030554331922ed12ea9da3ef51cd64b5c40
CRs-Fixed: 2522133
Implement hal_rx_msdu_end_da_is_mcbc_get based
on the chipset as the macro to retrieve
mcbc value is chipset dependent.
Change-Id: I860d259515c31345501080577d7a34beb97e5f60
CRs-Fixed: 2522133
Implement hal_rx_get_rx_fragment_number
based on the chipset as the macro
HAL_RX_MPDU_GET_SEQUENCE_NUMBER is
chipset specific.
Change-Id: I967190fa3a55d45f46760f58eab5007bf5fa908f
CRs-Fixed: 2522133
Currently after runtime resume all SW2TCL data and reo cmd
srng rings hp and tp value are flushed. In case of IPA
offload case SW2TCL3 righ hp value will be updated by IPA
and not by host. In case of runtime pm enable host is
setting the value to zero as part of runtime resume which
results in incorrect hp value of SW2TCL3. As part of this
change set flush event for rings which are accessed by host
during link down state and after runtime resume flush the
rings for which flush event is set.
Change-Id: I5c9afa708277cf3a6e6d5ef99447bc21f88cfdcf
CRs-Fixed: 2514621
added stats counter to check invalid release reason other than
FW and TQM in tx completion path.
added assert to make sure host is not releasing descriptors with NULL
address.
Change-Id: I3a30bd0f0c3954ed6435489d9b21f16201d1b840
Disable PN error handling in REO Queue descriptor setup.
This is different from pn check enable.
When PN error handling is enabled, if a PN check fails
REO queue descriptor sets pn_error_detected,
All the subsequent packets will be exceptioned with REO error code 13
till SW resets the pn_error_detected.
SW is not doing any special handling when PN error handling is enabled
Hence disabling flag in setup time instead of resetting/updating
reo queue descriptor as update is an uncessary overhead.
Change-Id: I21e40b6f685e50630fcc4413f6cd27e5ed9ff66d
1. Assign correct first msdu payload
2. Reset mpdu fcs ok bitmap upon reception of next ppdu
3. Free rx_ppdu_buf_q in error cases
Change-Id: I4f2e687d51d1e10693adc9cfcdee49190ba6815c
CRs-Fixed: 2502889
Add device ID change and target type checks for pine.
Also remove memory war added for Hk emulation.
Change-Id: Idf531a48a03202d4fb241a92a1d671ee2b94cfbd
CRs-fixed: 2453899
Read extra bits of fcs okay bit map from
RX_PPDU_END_USER_STATS_EXT TLV and use the same
to send first fcs okay packet in case of M COPY
CRs-Fixed: 2499150
Change-Id: I1a25971ea789dd7fddddb312af8a18a4cccdc178
Tags are programmed using wlanconfig commands. Rx IPv4/v6
TCP/UDP packets matching a 5-tuple are tagged using HawkeyeV2 hardware.
Tags are populated in the skb->cb in the REO/exception/monitor data
path and sent to upper stack
CRs-Fixed: 2502311
Change-Id: I7c999e75fab43b6ecb6f9d9fd4b0351f0b9cfda8
When the scheduler thread initiates the WMA_SET_BSSKEY_REQ
we send CMD_UPDATE_RX_REO_QUEUE to REO srng. This is done by
posting a descriptor to the reo command ring and then we
update the HP so that the HW can consume the descriptor.
Avoid accessing HP shadow address when we are in runtime
suspend state. Perform a hif_pm_runtime_get to resume the
link and access the shadow register and once done initiate a
hif_pm_runtime_put to allow device to go into runtime
suspend.
Change-Id: I24c3e046a5769f03a0f1969360cccdbe55b81d45
CRs-Fixed: 2495720
Add code to replace usage of void pointers from
HAL layer and instead use appropriate opaque pointers
Change-Id: Id950bd9130a99014305738937aed736cf0144aca
CRs-Fixed: 2487250
Add code to remove void pointer usage for hal_srng
and use opaque pointer dp_hal_ring_t instead.
Change-Id: I6907f7376d7fe3c9180b8795bd96f49fead2ec64
CRs-Fixed: 2484404
Make change to remove usage of void pointers for
ring descriptors and instead use a opaque pointer
dp_ring_desc_t.
Change-Id: Ia1e9a3da9eaa3cccf297b2135b52a72f2fe21431
CRs-Fixed: 2484409
Add code to remove void pointer usage for hal_soc
and introduce opaque pointer to be used intead of void
from dp layer into hal layer
Change-Id: Ia38571174c6ed79558d0f0c9cd1a0f4afaa66483
CRs-Fixed: 2480857
Reducing the log level of debug log to avoid console logging
and instead get it on the cnss diag log.
Change-Id: Ie5a1eb6f45ffa97790d91528a173b16319ec760b
CRs-Fixed: 2486057
In register select window if the register offset falls
in the last stored register window in driver, register
window remap is not done. There is a case if platform
driver accesses the hardware registers and remaps the
register window, then driver wont be aware of this and
have the wrong cached register window. So when driver
tries to write or read it selects the wrong register
window and accesses wrong register address. So fix this
by always doing the register window remap.
Change-Id: Ic38cc8cc3d9d82a3534f5ea356027db324c9fe13
CRs-Fixed: 2477771
Added new hal folder for pine. Included hkv2 functions whereever possible
to make sure there is not much code duplication.
Change-Id: I13247beb1af0b250f8e1bf182005f2513bdf9902
