For IFE only use-cases bump up the max number of configs
from 25 to 30, to support dual IFE requirements on Kailua.
CRs-Fixed: 3163468
Change-Id: Iffa5735fba3f8271b47ad368437b9174244ef889
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
Due to the scheduling delay, We are seeing back to back
two top half for buff done for 2 different requests
but we were expecting the bottom half after 1st top half.
We update the last consumed address in the bottom half so
we have 2nd req buffer address in last consumed reg as
we received 2nd req top half before 1st req bottom half.
We increment num_ack variable of 2nd request in case
of 1st req buff-done as it had 2nd buffer address in
last consumed address.
Ack is going beyond during the 2nd req buff-done.
This check will prevent duplicate acknowledgment increment.
CRs-Fixed: 3165255
Change-Id: I9ea3bca2a782bae6017565f30162484adf2fc789
Signed-off-by: Chandan Kumar Jha <quic_cjha@quicinc.com>
Select the clock corner of tpg source clock based on the input clock
received in the globalconfig command.
CRs-Fixed: 3164948
Change-Id: Ib945e0f82790d3a33ac5028850ef55a806c84784
Signed-off-by: Rishab Garg <quic_rishabg@quicinc.com>
For RDI only context EOF is not notified; it should be
notified, for the corner case if the flash is
configured to apply at EOF then it will block apply for
ISP on SOF as well until the EOF is notified, this
change adds EOF notification.
CRs-Fixed: 3091241
Change-Id: If6d974d092d640d9def89bbcf7a88fba0d85579b
Signed-off-by: Tejas Prajapati <quic_tpraja@quicinc.com>
Currently we allocate the memory for CDM GENIRQ command
within the Kernel on every stream on. Presil framework
do not have an ability to transfer the kernel only buffers
to the user daemon. For that reason we need to add support
to use the user allocated command buffer instead of the
kernel generated memory to add the GenIRQ cdm command
while submitting BLs. This change also helps to reduce
the stream on and stream off latency by not having to
allocate and free the GENIRQ memory on every stream on and
stream off respectively.
CRs-Fixed: 3115399
Change-Id: Ic159efd56fb9c4480ed1eb25cf2c058cbb914332
Signed-off-by: Jigar Agrawal <quic_jigar@quicinc.com>
Add bring up sequence header and driver support
for SM8650.
CRs-Fixed: 3149299
Change-Id: I072f3dd57f99c1625f58e90711e6908e6e97efe9
Signed-off-by: Jigar Agrawal <quic_jigar@quicinc.com>
Add support for more than one AON cameras for SM8650 target.
CRs-Fixed: 3149294
Change-Id: I842317ab59812109785a026fd0f728baf837b27f
Signed-off-by: Jigar Agrawal <quic_jigar@quicinc.com>
Modify sequence of CDM page fault handling to include pausing
cdm, setting global CDM PF bit, and streaming off all clients.
It also reduces PF handling latency by omitting CDM HW reset when
calling CDM stream off. While handling page fault, the faulted CDM
hw would not service all APIs to clients (except release) until all
clients release the CDM.
CRs-Fixed: 3156647
Change-Id: I3532bf68ba59800b2084dee252d7fd0807e0c68a
Signed-off-by: sokchetra eung <quic_eung@quicinc.com>
Fix error log in cci core so arguments match formatter.
CRs-Fixed: 3127448
Change-Id: I0af1121349868fc9b543a48d95429d267ab2cf26
Signed-off-by: Joshua Florez <quic_jflorez@quicinc.com>
RDI LCR variable is defined as bool in place of uint32_t causing
corruption of value.
This commit fixes this issue.
CRs-Fixed: 3153295
Change-Id: Ibbdd6617b4f738a6e047938e51d5bd613749854b
Signed-off-by: Gaurav Jindal <quic_gjindal@quicinc.com>
Separated ISP register dump from LDAR dump, fixed issue where LDAR dump
would fail if no active requests found, removed excessive logging function
call in ISP state monitor dump, fixed pending request/applied request dump
order to match tags in context utils, added more info from ISP stream.
CRs-Fixed: 3142549
Change-Id: Iaf25c0313714b5a776e3db81c11e96c7762d0f6e
Signed-off-by: Joshua Florez <quic_jflorez@quicinc.com>
Add and implement sysfs parameters to inject errors to
camera HW on demand through UMD for IFE,ICP and JPEG.
CRs-Fixed: 3115857
Change-Id: I4376fe31016cd81ad7e6f04cbc55e8ce010a6154
Signed-off-by: Pranav Sanwal <quic_psanwal@quicinc.com>
Currently, for sfe cases, we are searching for ife src corresponding
to ife rdi out resource, which is bound to fail. Add sfe rdi out
resources to map to ife src resource, which can be used in vfe top
to configure pdaf input config.
CRs-Fixed: 3149309
Change-Id: I51ca142bfa4a17ce10a18ce764799f46e029c347
Signed-off-by: Mukund Madhusudan Atre <quic_matre@quicinc.com>
Currently, we are writing reset values to frame/line/pxl drop
pattern and period registers at stream on, which is not required.
Also, this can overwrite any init config that user space might be
programming. Skip writing these registers in csid.
CRs-Fixed: 3144774
Change-Id: Iea253345467e12c068ab2c938ca8aadc591997ce
Signed-off-by: Mukund Madhusudan Atre <quic_matre@quicinc.com>
- Added Voting Option for APP Port send from UMD.
- Adding Path type and transaction type for CRE.
CRs-Fixed: 3081144
Change-Id: Id5e8eb8d41cc2354d76f9dbbad8dfb3e09cf66a3
Signed-off-by: Alok Pandey <quic_akumarpa@quicinc.com>
Signed-off-by: Ayush Kumar <quic_ayushkr@quicinc.com>
Modify IFE timestamp calculation to use a single qtime-to-boottime offset
value for all cameras. This will allow more precise timestamp comparison
between cameras.
CRs-Fixed: 3050973
Change-Id: Ic16864f544ad88e0215ae4d05a077d874af78fe9
Signed-off-by: Li Sha Lim <quic_lishlim@quicinc.com>
For ePCR/PCRs allow different combinations of scratch buffer
and ZSL buffer to be applied for different SFE/IFE ports.
CRs-Fixed: 3110947
Change-Id: I11677deaaa820955a2bc408bf90a848660ab831a
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
In RDI only usecase, if we get RUP and buf done
late, then we will enter bubble substate. In
current logic, we will move to SOF substate if
we get SOF in bubble substate, it causes the
buf done of bubble req can't be received. Since
we don't have valid interface for buf done in
SOF substate.
This changes don't move substate to SOF if we
are processing bubble.
CRs-Fixed: 3126554
Change-Id: I955173f12b5c1f5a699fa102e1ca6c82913c86e4
Signed-off-by: Depeng Shao <quic_depengs@quicinc.com>
When smmu page fault happen, buffer handle in smmu log
is always not identified due to using the index defined
in smmu. The index is smmu client index, buffer handle
should use the index defined in memory.
CRs-Fixed: 3096436
Change-Id: I69e5014c88ec507e31c6394564fb1990f5ae2d25
Signed-off-by: zhuo <quic_zhuo@quicinc.com>
On CSID unpack and WM pack, align the sensor width to 8,
when WM packs the data when writing to DDR.
CRs-Fixed: 3140614
Change-Id: Ie994cbe45b5b87c8a50a4ae2a9929dee6a31860e
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
Increase “OPE_MAX_CDM_BLS” to 32 from 24 and MAX_STRIPES to
64 from 48.
CRs-Fixed: 3082993
Change-Id: I9e3631cc86c5e10e4e2020d4a9b2264ea282e437
Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com>
Few sensors needs to unlock register bank for reading
sensor ID from sensor register for probe. And this change
adds support to write sensor registers in probe cmd just
after power on and before reading the sensor ID.
CRs-Fixed: 3111822
Change-Id: Iee2e6bd0ba896a0a2d0c4cc23fe272ba4aae3ab2
Signed-off-by: Stark Lin <quic_starlin@quicinc.com>
The 'l_device' pointer in __cam_req_mgr_destroy_subdev is
set to NULL after freeing but this is done on a
local copy of the variable in stack. This results in
double-free when this function is called again. To avoid
this, pass 'l_device' pointer by reference and assign it
to NULL after freeing.
CRs-Fixed: 3120468
Change-Id: If2dde6f1c702bee26a3c8a68c2f45bafbf0f7cd6
Signed-off-by: Nirmal Abraham <quic_c_nabrah@quicinc.com>
Since the CCI error isn't fatal error during probing sensor,
so we can just print an info log for the CCI error.
CRs-Fixed: 3118450
Change-Id: Ie980c9eb37e410b07c434a7a304ab1c18925319b
Signed-off-by: Depeng Shao <quic_depengs@quicinc.com>
This fix addresses the current problem of ICP communicating through HFI
prior to HFI being set up.
CRs-Fixed: 3130279
Change-Id: I306b6dd85eb08b7c5c6f49f9f2aad05a42b394bc
Signed-off-by: Li Sha Lim <quic_lishlim@quicinc.com>
On CSID encountering a fatal rx error, notify phy to update it's
aux settings for the given data rate when it streams on the
next time. The phy device will book keep all the data
rates that need updated aux settings and on all the
occasions they are streamed on the updated aux settings will
be configured. This is supported for all data rates
from 1.2 - 2.35 GSpS. The change also adds a debugfs in phy driver
to disable aux settings update altogether.
CRs-Fixed: 3120043
Change-Id: Ia1ea3b9278c2eb918a527ee3d7b1ecfe53c4f2c2
Signed-off-by: Jigar Agrawal <quic_jigar@quicinc.com>
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
Instead of correct link handle, if some other handle like
dev handle is passed then it may access some other data space.
To avoid such scenario, need to check whether link handle
passed by ioctl is same as retrieved link handle.
CRs-Fixed: 3120454
Change-Id: Idff2e3c25b60563788ffb426c7cabc367c3c97f8
Signed-off-by: Yash Upadhyay <quic_yupadhya@quicinc.com>
Add back in check for ddr memory type to distinguish between DDR4/5
memory types.
CRs-fixed: 3136181
Change-Id: Ia152cde2786bf6e3da172d2b7046f9871d4f8e3c
Signed-off-by: Karthik Jayakumar <quic_kjayakum@quicinc.com>
Signed-off-by: Wasim Khan <quic_wasikhan@quicinc.com>
Fix the CPAS Start and CPAS stop call sequence
for the Sensor power up. Also, only start and stop
the CPAS when we really want to write to the
AON-Main Camera Mux register.
CRs-Fixed: 3134267
Change-Id: If73ddc838d59a71f0e6cd21d390c7e603c42b2d6
Signed-off-by: Jigar Agrawal <quic_jigar@quicinc.com>
Without this, tpg is keeping refCount on titan top gdsc and
thus causing qchannel handshake side effects.
Sequence:
1. TPG calls cpas_start, increments refCount on gdsc with
soc_enable_resources
2. run usecase
3. TPG missing disable_soc_resource
4. TPG calling cpas_stop : which shuts down qchannel
5. When next iteration starts, because gdsc is still on from
previous session, cpas top is not getting reset state
registers - thus keeping qchannel still in shut down state.
qchannel goes to good state if gdsc is actually turned off
and then turned on.
CRs-Fixed: 3131613
Change-Id: Iacb837f7ee3fd7d6b094d0271d0f2d9c15f0b306
Signed-off-by: Pavan Kumar Chilamkurthi <quic_pchilamk@quicinc.com>
For some chipsets, qchannel handshake needs icp clk to be
enabled. Add support to enable icp clk while qchannel
handshake by adding as optional clk in cpas node. Whether
to enable icp clk or not is controlled through workaround
list populated for each chipset.
Add mechanism to retry qchannel acceptance if the first
auto try has failed, by explicity writing 0x1 to qchannel
ctrl register. This will bring back qchannel to good state.
CRs-Fixed: 3131613
Change-Id: Ie39a9789b2eb1bf9c0f6adb26fe6d6e1823eff70
Signed-off-by: Pavan Kumar Chilamkurthi <quic_pchilamk@quicinc.com>
Add CDM core registers dump functionality for
the scenariors where the cdm reset timesout and
the workqueue is delayed.
CRs-Fixed: 3130212
Change-Id: Ib79bb24164c77082eacfbecd14795b726bb14201
Signed-off-by: Jigar Agrawal <quic_jigar@quicinc.com>
bufq mutex can be destroyed at unmap, if other thread
is trying to lock the bufq mutex it can result in
bad magic number. To avoid such race condition
check bitmap with protection of global mutex lock.
CRs-Fixed: 3120472
Change-Id: Id95be0faa5b0d921c4a0370ea5d2f3b23c229280
Signed-off-by: Tejas Prajapati <quic_tpraja@quicinc.com>
Add support to report causes of fence errors for ICP and IFE.
The change also reports ICP critical failures like WD bark
and system error to userspace.
CRs-Fixed: 3035452
Change-Id: I699621ae71e0f8902cb7b9d42203effd2e2e40de
Signed-off-by: sokchetra eung <quic_eung@quicinc.com>
Change flush request active and flush request pending arrays from
static of size 20 to dynamically allocated size based on current
pending and active request lists.
CRs-Fixed: 3046003
Change-Id: Iaa1179881d786359dbe9d37411a6ef3ae8038227
Signed-off-by: sokchetra eung <quic_eung@quicinc.com>
Currently main/aon control operation is getting trigger explicitly
from probe control with the reason that Probe IOCTL is exclusive to
sensor core. This operation is required for making sure to get the
control to hlos before reading slave id. Further post probe operation
main/aon control selection is managed by csiphy driver at the time of
acquire and release ioctl call. This will block the main camera
operation after probe ioctl successful and before csiphy acquire ioctl
call. There are some usecase where sensor needs to perform several
operation independently. To add this support moving the main/aon
selection call from probe only ioctl operation to power_up/down call
flow. This call is made upon when it is required to operate on sensor.
This change will help to give AON sensor more flexibility to perform
independently. Further CSIPHY also have the same selection process
in it's acquire ioctl operation which can help to make the hlos end
selection in combo mode scenario.
CRs-Fixed: 3084672
Change-Id: Ic1c6ad41e35605a2291e7e50ff0fe94a0ab30624
Signed-off-by: Jigarkumar Zala <quic_jzala@quicinc.com>
Signed-off-by: Jigar Agrawal <quic_jigar@quicinc.com>
If HFI init times out, log ICP status and CSR registers.
CRs-Fixed: 3110947
Change-Id: I611c29ee1b48f210f76750e57f38e260278b6812
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
When set, buffers will be mapped within 32-bit region
address space and in patching, if Shared or CmdBUffer is
not set for such buffers - patch the value with right shift
by 8. kmd does as below.
Map:
Shared or CmdBuffer : Mapped within 32bit.
HwAndCDMOrShared : Mapped within 32bit
others(HwAccess) : Mapped within 40bit
Patching:
Shared or CmdBuffer : as is
HwAndCDMOrShared : iova >> 8
others (HwAccess) : iova >> 8
Shared/CmdBuffer takes precedence over HwAndCDMOrShared.
CRs-Fixed: 3128094
Change-Id: Ifd9f5beaf2659f77544cd0722ef7f60d6c0684a7
Signed-off-by: Pavan Kumar Chilamkurthi <quic_pchilamk@quicinc.com>
Update the csiphy header 2.1.2 with the new bring up
sequence revision 11.
CRs-Fixed: 3127494
Change-Id: I9a3579ecd2fc2274cf9913af0ef054cc62343b0e
Signed-off-by: Jigar Agrawal <quic_jigar@quicinc.com>
While saving iova address, we were saving into uint32 which is
truncating the address. When this address is programmed to hw,
its causing page fault. Fix by saving the iova first into
dma_addr_t which is uint64 and then calculate base and offset
register values to program to hw.
CRs-Fixed: 3128094
Change-Id: Ie8dc8cbd9848267b7b50db5ef987bd06518cc357
Signed-off-by: Pavan Kumar Chilamkurthi <quic_pchilamk@quicinc.com>
To utilize more than 32-bit address space, clients need to call
dma_set_mask_and_coherent API. When called with particular value,
the max address range thats mapped on this context bank is
min of this mask value and value_from_iommu-dma_addr_pool.
CRs-Fixed: 3128094
Change-Id: Ib48dc0b00f8e915ca7faa367bec7473aed9931b4
Signed-off-by: Pavan Kumar Chilamkurthi <quic_pchilamk@quicinc.com>
Add support to enable SFE/IFE perf counters by allowing
user to configure the counters. By default the counter
values are dumped at EOF.
To configure the counter-
adb shell cat /sys/kernel/debug/camera/ife/isp_perf_counters
adb shell "echo "ife_1_2162693" >
/sys/kernel/debug/camera/ife/isp_perf_counters"
A read on the debugfs file will list the available counters
on the target for the different HW blocks.
The change also adds support to configure CSID test bus.
adb shell "echo <reg_val> >
/sys/kernel/debug/camera/ife/ife_csid_testbus".
CRs-Fixed: 3110947
Change-Id: Idc3952e64c943acd1d1893ed24eea88cf9908100
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
Force callers to say if they are using 36 bit address patching or not.
CRs-fixed: 3121782
Change-Id: I4dee25e3f73104a1be043fe18a295cd4f8447821
Signed-off-by: Karthik Jayakumar <quic_kjayakum@quicinc.com>
Print out WM information on CCIF violation.
CRs-Fixed: 3121755
Change-Id: I0fffd8cf4bc7af660f120ba1df8917cd95af64b4
Signed-off-by: Anand Ravi <quic_ananravi@quicinc.com>
Corrects the variable debug print statements for expanded memory case
in IFE.
CRs-Fixed: 3120109
Change-Id: I08e2849db21459ebaecec68a7340d8d103562743
Signed-off-by: Karthik Jayakumar <quic_kjayakum@quicinc.com>
