Commit Graph

2464 Commits

Author SHA1 Message Date
qctecmdr
4f0632e798 Merge "disp: msm: dp: check for dp link clocks before accessing dp registers" 2021-08-20 11:01:30 -07:00
qctecmdr
19e36887d2 Merge "disp: msm: remove use of DMA attributes LLC_NWA and Upstream Hint" 2021-08-19 18:45:48 -07:00
Nilaan Gunabalachandran
d7172c5009 Revert "disp: msm: sde: program qseed through ahb"
This reverts commit 3617430855.
This change will re-enable qseed programming through lutdma.

Change-Id: I57b897088eeccddc63ee010e296b5d4622d27a9f
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2021-08-19 13:15:54 -07:00
Vara Reddy
c57fe2034a disp: msm: dp: check for dp link clocks before accessing dp registers
Add safety checks to check for dp link and core clocks before accessing
the main control registers during dp teardown or dp setup.

Change-Id: Ic80050b7c1cec59d7fc27a1c5f12fa1b244f86fb
Signed-off-by: Vara Reddy <varar@codeaurora.org>
2021-08-18 22:24:32 -07:00
qctecmdr
b6b3b01190 Merge "disp: msm: select non secure context bank regardless of dma buf flags" 2021-08-18 16:48:48 -07:00
qctecmdr
bb36f9fd40 Merge "disp: msm: sde: add helper to check VM hw availability" 2021-08-18 16:48:48 -07:00
qctecmdr
eeb3606b4c Merge "disp: msm: sde: correct rounded corner bottom start check" 2021-08-18 12:49:56 -07:00
Anjaneya Prasad Musunuri
a3f8e9ab8f disp: msm: sde: correct rounded corner bottom start check
Bottom start must be lesser than display height by at least
one line.

Change-Id: I36fbf68ee6733c020f235dca04c4b00c1e5a2312
Signed-off-by: Anjaneya Prasad Musunuri <aprasad@codeaurora.org>
2021-08-17 23:09:08 +05:30
Samantha Tran
2c2224bdf3 disp: msm: remove use of DMA attributes LLC_NWA and Upstream Hint
Remove DMA_ATTR_IOMMU_USE_LLC_NWA and DMA_ATTR_IOMMU_USE_UPSTREAM_HINT
attributes as they are no longer needed since io-coherency is enabled.
Passing this attribute is a no op since buffer is io-coherent and will
be mapped with a write allocate policy contradicting intention
of that attribute.

Change-Id: I882f148d770c795eb005c5391171a6280c083d37
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2021-08-16 12:00:33 -07:00
Krishna Manikandan
9f41ad11b3 disp: msm: sde: add null check for drm file in msm_release
Drm file is not set to NULL after freeing it from drm
release. This can result in use-after-free issues in
some scenarios. Add a mutex lock and other proper null
checks to prevent such issues.

Change-Id: Ic35b0a76166b0f47a354b1737e6f4c3ac1437ed4
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
2021-08-16 06:31:40 -07:00
qctecmdr
88877f3037 Merge "disp: msm: sde: add sde data to va minidumps" 2021-08-15 18:31:12 -07:00
qctecmdr
d55bc8d204 Merge "disp: msm: dsi: acquire panel lock for command transfer through debugfs" 2021-08-15 18:31:11 -07:00
qctecmdr
4ec64c1672 Merge "disp: msm: sde: compute timeouts based on refresh rate" 2021-08-13 20:50:46 -07:00
qctecmdr
4b778c82ce Merge "disp: msm: sde: update unmult offsets" 2021-08-13 20:50:46 -07:00
qctecmdr
c9fb272a73 Merge "disp: msm: dsi: allow cmd-engine enable/disable HW op at all times" 2021-08-13 20:50:45 -07:00
Satya Rama Aditya Pinapala
adfbc98df7 disp: msm: dsi: acquire panel lock for command transfer through debugfs
To ensure that no other command transfer is in progress, during DSI
TX operation through debugfs, panel lock needs to be acquired.

Change-Id: I8d3871e32277840867d9494720e77df3566e30d3
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
2021-08-13 13:18:44 -07:00
qctecmdr
7986d0d1b1 Merge "disp: msm: dp: add support for 3.75:1 compression" 2021-08-13 08:58:26 -07:00
Steve Cohen
7f3b2f0a4b disp: msm: sde: add helper to check VM hw availability
Add a utility function to check if HW has been handed over to
another VM.

Change-Id: Ic36ca1e7f15f7608e69d69fc3f4e7ad40be15704
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2021-08-12 22:58:30 -04:00
qctecmdr
7ec82f88a8 Merge "disp: msm: add qsync refresh rate support per mode" 2021-08-12 14:10:43 -07:00
qctecmdr
e50cd5cb61 Merge "disp: msm: sde: remove clearing cur_master in encoder enable function" 2021-08-12 14:10:42 -07:00
Steve Cohen
9690b545df disp: msm: sde: prevent custom ioctls from accessing unowned HW
Early wakeup ioctls from perf HAL driver can access display HW
registers and come as a sideband to atomic commits. Since the
atomic validate checks are not part of this code path it's
possible for HW access to occur during a trusted UI session.
Prevent this whenever the HW is not under this VM's ownership.
Also, move the VM ownership check for the register/deregister
event ioctl to cover both the CRTC and connector events since
new connector events are being added which can access HW.

Change-Id: I39660ae60e7e8f8a405e819c43ec42fbac3f492a
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2021-08-11 15:38:27 -04:00
Nilaan Gunabalachandran
8724924e6e disp: msm: sde: update unmult offsets
Unmult feature is currently using offsets from previous targets.
This leads to unexpected alpha transparency errors on screen.
This change updates the new offsets based on hw version and
retains the original offsets for backward compatibility.

Change-Id: Icdba050371a583f1a20b91a451be3324de12c2cf
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2021-08-11 11:20:47 -04:00
Prabhanjan Kandula
642c86fee9 disp: msm: sde: compute timeouts based on refresh rate
Current timeout values in sde driver for vblank, kickoff and
frame complete timeouts are fixed and can be much lower than
a vsync incase of low refresh rate display. Compute timeouts
based on refresh rate for low refresh rate displays.

Change-Id: I9dda41feb15446de7451824e185321de421ad575
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
2021-08-10 14:51:41 -07:00
Lei Chen
b151e6660b disp: msm: sde: remove clearing cur_master in encoder enable function
SDE IRQ callback can run in parallel thread to modeset after removing
pp_done wait before pre_modeset.
If cur_master is cleared in encoder enable function and irq callback
is triggered at the same time, the irq callback could not be handled
properly as cur_master is NULL.
So remove clearing cur_master in encoder enable function to avoid the
race condition between modeset and irq callback.

Change-Id: I2059c699a68838b3c9f6a7dd658a35f178b18c42
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
2021-08-09 10:58:38 +08:00
Rajkumar Subbiah
eebce2ae4c disp: msm: dp: add support for 3.75:1 compression
Currently the DP driver always uses a compression ratio of 3, if
DSC is enabled. So if the sink supports 30bpp, the compressed
output is set to 10bpp. But since the hardware supports
compressing this to 8bpp, it would require less link bandwidth
than 10bpp compressed output. For compliance testing, the
test equipment limits the link bandwidth based on the most
efficient compression ratio and for some resolutions there
is not enough link bandwidth for 3:1 compression.

This change always sets the compression output to 8bpp to
minimize the link bandwidth utilization.

Change-Id: Ifa6129444c2bab4e9c357ddfe49f76efa5b04be0
Signed-off-by: Rajkumar Subbiah <rsubbia@codeaurora.org>
2021-08-05 20:26:34 -04:00
Rajkumar Subbiah
17997f6098 disp: msm: dp: update TU calculator for DSC and RB2 support
Updating the TU calculator to fix the formulas for the following
two use cases:
* 3.75:1 DSC compression
* Modes with RB2 (reduced blanking) timing.

Change-Id: I295e3fc252691a7fb42b610101da32c9f31d1855
Signed-off-by: Rajkumar Subbiah <rsubbia@codeaurora.org>
2021-08-05 20:26:34 -04:00
Yashwanth
64b732f335 disp: msm: add qsync refresh rate support per mode
This change adds support for qsync min refresh rate per
timing mode and populates qsync min refresh rate based
on the current fps when qsync is enabled.

Change-Id: I191d1d72e95dd065c8c0b56a6100104c00c6d8f6
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2021-08-05 15:37:20 +05:30
qctecmdr
6bf96605eb Merge "disp: msm: sde: cache disable cp properties during last close" 2021-08-03 19:17:54 -07:00
qctecmdr
8a2ddb713f Merge "disp: msm: sde: expose number of rounded corner blocks" 2021-07-30 10:14:21 -07:00
qctecmdr
f7e7964840 Merge "disp:msm:sde: correct the brightness bound check" 2021-07-29 19:41:43 -07:00
qctecmdr
f4f3c29d70 Merge "disp: msm: dsi: fix RFI mode set detection" 2021-07-29 14:48:53 -07:00
Gopikrishnaiah Anandan
610b71feb9 disp: msm: sde: cache disable cp properties during last close
When all instances of driver fd's are closed by user-space client, drm driver
will be closed. When last close of driver is called, custom reset properties
api will be called where driver should cache the properties that it wants to
clear. Current behavior of color processing driver is to clear hardware
configuration instead of caching which can cause crashes if clocks are off.
Change updates the driver to cache the pending disable and update hardware
during display commit.

Change-Id: I9703f860ed0ae3c859d6fc3995b58be13203f259
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
2021-07-29 13:56:02 -07:00
Amine Najahi
0c8c956b1f disp: msm: sde: expose number of rounded corner blocks
Expose the number of RC hardware blocks to handle multi-display
use cases where RC feature needs to be enabled only if there
are sufficent RC hardware blocks available.

Change-Id: I37fe3ee4ac72894d9d51e832551d3fc19c0354b8
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
2021-07-29 15:10:24 -04:00
qctecmdr
bc1b84e6fc Merge "disp: msm: sde: update rsvp_cur when poll is enabled for rsvp_nxt" 2021-07-29 10:12:51 -07:00
Amine Najahi
e3c76571dc disp: msm: dsi: fix RFI mode set detection
Currently mode fixup function is called multiple times
in the same commit. This causes invalid combination of
DSI mode flags to be set when there is an RFI change
with proch compensation feature enabled.

This change modifies the mode switch condition for DMS
to compare internal dsi mode and flags and fixes the
dynamic clock change detection by using a single variable.

Change-Id: Iaf9c8ca7c6a27f26aefead399bc93fbbb02b404b
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
2021-07-29 07:43:27 -07:00
Amine Najahi
1881acdb2b disp: msm: dsi: publish RFI porch values for rate matching calculation
Currently when RFI is used on a video mode panel the horizontal or
vertical front porch values can be adjusted to maintain a constant FPS.
When this feature is enabled, driver is not propagating the new
htotal or vtotal values to usermode for accurate BW and MDP clock
calculation, which may lead to underrun in some usecase.

This change publishes beforehand all the RFI related timing
such as compensation type, hfp or vfp and clock values for
each mode for accurate BW and clock calculation.

Change-Id: Ib89c5e318fe978b0ae2215dedc430e057a9a81b9
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
2021-07-29 10:35:27 -04:00
Ping Li
b7506f0222 disp:msm:sde: correct the brightness bound check
The brightness value from backlight device is OS brightness, not panel
backlight value. This change corrects the brightness bound check to
check against the OS brightness max value instead of panel backlight max
value. This change also move the bound check in dsi display to make sure
the max backlight value send to panel is within the expected range.

Change-Id: Ic9e3ba69700ae4c0e950cb665837a1f0a1317b26
Signed-off-by: Ping Li <pingli@codeaurora.org>
2021-07-28 12:32:45 -07:00
qctecmdr
b04d8af8da Merge "disp: msm: dsi: update DSI PHY HW programming" 2021-07-28 06:06:16 -07:00
Jayaprakash Madisetty
0a56792383 disp: msm: sde: update rsvp_cur when poll is enabled for rsvp_nxt
This change updates rsvp_cur pointer to latest to avoid use
after free issues. rsvp_cur pointer can be freed in few cases due
to the unlock, wait and lock of rm_lock present in
_sde_rm_poll_get_rsvp_nxt_locked.

Change-Id: I389048188e8a615edc3e75dd1102d4ca8c74af65
Signed-off-by: Jayaprakash Madisetty <jmadiset@codeaurora.org>
2021-07-28 05:40:24 -07:00
Samantha Tran
4792530219 disp: msm: select non secure context bank regardless of dma buf flags
dma_buf_get_flags is deprecated. Rather than using its updated API, avoid
checking flags and instead default to non secure context bank always.
Logic is already in place to detach from non secure and attach to secure
if needed based on plane property.

This change also removes the check for cached buffers since moving forward
all buffers will be cached so there is no need for this.

Change-Id: I64c28b1d6f4b6864dd56764027ce8964b174e715
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2021-07-27 13:47:26 -07:00
Jayaprakash Madisetty
dad1b5f51e disp: msm: sde: handle spec fence bind failure case as non fatal
Add changes to handle speculative fence bind failure case with
invalid userfd as non fatal scenario and stage white frame in such
case.

Change-Id: I1386bfc5ecb5107ab100be220c24597f883d9bd6
Signed-off-by: Jayaprakash Madisetty <jmadiset@codeaurora.org>
2021-07-27 13:22:51 +05:30
qctecmdr
2a5878a83f Merge "disp: msm: sde: Correct Demura memory parsing for single address per region" 2021-07-24 14:43:41 -07:00
qctecmdr
3d45203d45 Merge "disp: msm: dp: clear mst edid cache for real monitor plugin" 2021-07-24 04:52:53 -07:00
qctecmdr
e72cdd796f Merge "disp: msm: dsi: prepare resources for cmd transfer at the start of the cmd packet" 2021-07-22 19:51:32 -07:00
Satya Rama Aditya Pinapala
095f5dd58a disp: msm: dsi: prepare resources for cmd transfer at the start of the cmd packet
For batched commands, prepare resources at the start of the command packet and not for the
command with LAST_COMMAND flag set.

Change-Id: Ibbb0d1d1acd4ddeebd07bf9dd6ea1a949edd8d02
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
2021-07-22 10:37:58 -07:00
qctecmdr
8ff5362a29 Merge "disp: msm: update register dump and debug bus memory allocation" 2021-07-21 21:20:52 -07:00
qctecmdr
2df9899db4 Merge "disp: msm: sde: add pr_fmt for SDE VM layer" 2021-07-21 21:20:52 -07:00
qctecmdr
48e71a3272 Merge "disp: msm: dp: account for fec overhead during bpp determination" 2021-07-21 07:18:36 -07:00
Christopher Braga
844e618c26 disp: msm: sde: Correct Demura memory parsing for single address per region
Demura memory region parsing incorrectly uses the display number
as an extraction index, causing failures in dual panel cases.
Update Demura memory region parsing to always use index 0 during
extraction as each defined region is designed to only declare
a single memory address.

Change-Id: I270f392b636148acd9b891bffcc3cf3d032eab70
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
2021-07-20 17:02:21 -04:00
Sudarsan Ramesh
1def76170d disp: msm: dp: clear mst edid cache for real monitor plugin
Currently edid cache is cleared only in the mst attention callback
flow i.e. if a monitor is plugged in/out of a mst dongle. If mst
dongle is plugged out directly, the edid cache is not cleared.
This change clears the edid cache also during the
connect/disconnect callback.

Change-Id: Icc4b4ca6a59f1ee32f7fe062831a3a19f4ab9f00
Signed-off-by: Sudarsan Ramesh <sudarame@codeaurora.org>
Signed-off-by: Sandeep Gangadharaiah <sandgang@codeaurora.org>
2021-07-19 10:40:22 -04:00