Add capability to read avr step for each timing mode. This will
be in addition to the existing avr-step-list which is defined
when dfps is enabled. Expose the avr-step as part of each
mode in connector caps to user-mode.
Additionally, change the avr_step connector property to enum
to give usermode just the capability to enable/disable avr-step
and not alter the step value as its fixed from the device tree.
Change-Id: I6d7f8e9fcf03f98abef7640fc741e5e1be8597a1
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Add DCS command to read the panel scan line value and associated
time stamp in nano-seconds.
Change-Id: I06a76d3a6c5ad7a2e7681413c741e5b97b34d73f
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Timing DB needs to be disabled after panel vnsyc.
Update the wait time to reflect difference in line time
between MDP and panel vsync.
Change-Id: Ib5282d67995e8379ead928218f31a8f9fe7fa978
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
DSI PHY isolation is unused and considered deprecated. Previous uses
were for power measurements and emulated platform support. Use on
emulated platforms has been supplanted by PHY PLL bypass.
Change-Id: I547681912ff82f0df09a1b98c671eac32c19412a
Signed-off-by: Alex Danila <quic_eadanila@quicinc.com>
devm_of_pwm_get is deprecated and need to change
to devm_pwm_get.
Change-Id: Ibeee90261ff40dc50b6a5e40e583bee11a5b177c
Signed-off-by: Maria Yu <quic_aiquny@quicinc.com>
Signed-off-by: Vara Reddy <quic_varar@quicinc.com>
This change adds support for bypassing hw access in DSI PHY/PLL
drivers which enables the DSI driver to run on emulation
platforms that might be missing those modules.
Change-Id: I3e83155a79d60f2357606746214d776cefabd651
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
Signed-off-by: Alex Danila <quic_eadanila@quicinc.com>
For calculating bit rate in cphy, we multiply bit rate by a factor of
7/16 where 7 is the number of symbols and 16 is the bits per symbol.
But we are currently not considering the 7/16 factor while calculating
minimum bit clk value for command mode which is resulting in a smaller
bit rate value than the minimum bit clk.
Bit rate should always be greater than the minimum bit clk which otherwise
can lead to discrepancies. Correct minimum bit clk calculation for command
mode, by multiplying a factor of 7/16 if cphy.
Change-Id: I39b202dcafe60e2047549f84ff9388b46ae490a5
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
This change fixes printk arguments in display driver which is
found with additional compilation flags and adds the compile
flags too.
Change-Id: Ic653591db49b49b9ce1ce04e7df89216772d0e71
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
Currently the panel esd_recovery_pending flag is cleared for every mode
set. The ESD recovery completes only after the suspend and resume. Clear
the flag only during power on commit.
Change-Id: I97e370feba0aad34558e4675168b4bcb7f5901ca
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
Added dsi ctrl version 2.8 support for pineapple hardware
Change-Id: If9beb77c53d70d94b498b5b837c26892a4df9089
Signed-off-by: Kirill Shpin <quic_kshpin@quicinc.com>
This change adds dsi display ramdump support when DEBUG_FS
is not enabled.
Change-Id: Ic6659a9380acd5eb55a3270d3e3b7016a9cd2bd7
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
This reverts commit 14e7e9b409346aa77fd08cca6eab85252d9ccabe.
Reverting this for now until we properly understand the reason
for command transfer timeouts that we are hitting for 5k panel.
Change-Id: I0390af66f9ca06abc1ebb81996bb683dea35beac
Signed-off-by: Vara Reddy <quic_varar@quicinc.com>
Avoid shutting down DSI PHY and lanes before entering into
idle collapse.
Change-Id: I62fb40c2398e544b08b8cb8788ac2dc1143a82ce
Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>
DSI PHY has various resets defined to reset analog, PLL and digital
portions. In current sequence, these resets happen after PLL is locked
which can result in introduction of jitter on PHY lanes.Reordering these
resets to happen before PLL is programmed to have intended clean start
of DSI PHY.
Change-Id: I4eb5c05ea0e6015a5447728b2845b49817411c50
Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>
Change increases cmd dma timeout to 1200 milliseconds from 200 milliseconds.
There are video mode panels which can support one frame per second, if pixel
data transfer is active, then our command transfer timeout should be atleast
1000 msec.
Change-Id: I3e8269febe3ed6e55ac9381a8de35e7d19fa3160
Signed-off-by: Vara Reddy <quic_varar@quicinc.com>
Allow TPG patterns to be displayed on command mode and
video mode panels.
Change-Id: Ie9ba9b404ceb965f8a06d1f19e932dd2e051983b
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
Currently we are always initializing PLL registers whenever PLL is
configured. Re-initializing PLL registers during dynamic clock switch in
case of cphy video mode is moving the PLL to some bad state resulting in
display freeze. Avoid this by restricting initialization of PLL registers
to only while turning on the PLL.
Change-Id: I09eacbb37fff4e0e91d226ac08e7d5a2bfbbfe26
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
The hs timer control settings can't match with dsi data transfer
requirement, so it may lead to timeout issue when running into low
frame rate, update this change to fix such issue for 30hz display
mode.
Change-Id: I01942a494f46e0023061a9d307a9d2ca1fd8159a
Signed-off-by: Yahui Wang <quic_yahuiw@quicinc.com>
pll_codes_region is not defined on TVM and not programmed.
So, adding TVM check to avoid parsing pll code data.
Change-Id: Ia6280ca3fc1b19866673a6767de465d17681add7
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
This change moves warning log to info log if secondary default panel
is not available.
Change-Id: Iad420a05c6440afdf0fcc5f7d33197eaf5c158c4
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
When display is left on from the bootloader, disp_cc driver will put a
proxy vote on clocks to maintain the hardware configuration of bootloader.
Once all the consumers have been probed, the dispcc driver will synchronize
the hardware state of the device to match the aggregated software state
requested by all the consumers using sync_state call.
If there is an idle power collapse or a suspend before sync state call,
branch clocks and in turn RCG will not get turned off during clocks
disable sequence because of the proxy vote of disp_cc driver. This can be
the case even if there is a vote from any other disp_cc consumers.
During a subsequent call to enable the clocks from DSI driver, we are
currently switching RCG parent to PLL and then turning on the PLL.
If the sync state call doesn't happen before we enable the clocks back,
we'll be setting PLL which is off as a parent to RCG that is on.
But ideally when RCG is on, both the old and new sources should be on
while switching the RCG parent.
Avoid this by turning on the PLL before switching RCG parent during clock
enable sequence.
Change-Id: I1597cf2c8095957cd2b2a20a72bf7199e0d61809
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
Acquire dsi_ctrl->ctrl_lock lock before programming dsi ctrl
registers. Failing this may lead to race conditions in register
programming.
Add missing mutex lock inside dsi_ctrl_host_timing_update().
Change-Id: Ic86cbe282333c0b4d63ae3d5b3356a5d24752203
Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com>
Pass the DRM_BRIDGE_ATTACH_NO_CONNECTOR flag when attaching the
bridge so that the bridge driver would not create another
drm connector.
Change-Id: I838bd87c40d0eea3df36187befeb7195fb87d5b3
Signed-off-by: Rahul Sharma <quic_rahsha@quicinc.com>
Avoid various possible nullptr dereferences.
Addresses various issues highlighted by static analysis.
Change-Id: I36d34d610b37bf2799a7e34cd1de8b909b5c0ae4
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
To toggle error interrupts, we currently read the DSI_INT_CTRL register,
toggle the DSI_ERROR_MASK bit and write back to the register. While doing
so we are also writing back 1 to any status bits set by HW, thus clearing
the status interrupts. Clearing the status bits should always be done as
part of interrupt handling, which otherwise can lead to command transfer
failures.
Avoid clearing status interrupts while error interrupts are toggled.
Change-Id: Iaae10c279f2341269ed49074448167e68ab7e13c
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
Sim panels are not working well with video mode, parse panel ack
disabled property to fix sim video mode identification issue.
Change-Id: Ife3b533d5a6db97618459dacf1f7ce8d3fc896bf
Signed-off-by: Yahui Wang <quic_yahuiw@quicinc.com>
Add line insertion support for sspp, this is used to support
display with external splitter. Line insertion logic checks
the difference between screen logical height and physical
height. If any difference is observed adds dummy and active
lines on screen.
Change-Id: Ieec322273df000a53fb39e05174c2d67c3c2da81
Signed-off-by: Rajesh kv <quic_kvrajesh@quicinc.com>
In transfer-time calculation remove fixed prefill lines assumption
and consider max of default prefill lines, prefill lines
specified from the panel timing info and Vtotal. For panels with
higher porches exceeding default prefill lines, alternate framedrops
can occur if transfer-time exceeds RSC static waketup time
as actual prefill lines are considered in RSC static wakeup timer
calculation. This change ensures transfer-time is within
RSC static wakeup time.
Change-Id: Ic489d69cf99cfb6750e871c7fc8197243f61acf3
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
This change adds a connector OP, that will be used to update frame
transfer time dynamically at the request from user space.
It also adds parsing for new device tree entries that set the minimum
and maximum trasnfer times on a mode basis. These min and max transfer
times are also published to userspace through the connector mode info
capabilities blob.
Change-Id: I12aedf96a51ff7feb2c5b3b1353d3c4ec8dcb068
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
Add DSI CTL MISR support for ctl 2.2 version. Reuse the same
debugfs nodes to setup/collect misr.
Change-Id: I3d8dfab093659ce53817d9511999c0c03cc33f62
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Refactor the function 'dsi_display_get_modes' to
reduce its complexity.
Change-Id: I1a8ecaa780e5070bac7fa40404677c0a8a5d7cd8
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
Mitigate errors to debug logs on non-parsed regulator look ups. Callers
can make use of the return value to handle failures.
Change-Id: Ib0ed869e92104ac7e859484b247ac99bf332fa5c
Signed-off-by: Jeykumar Sankaran <quic_jeykumar@quicinc.com>
Fix the Watchdog timer load value calculation with jitter feature.
Change the long term jitter value check to have jitter < 10.
Change-Id: If834e16d3b8fad5009642e479f529fa5b7cf2d17
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
* quic/display-kernel.lnx.5.10:
disp: msm: sde: avoid error during fal10_veto override enablement
disp: msm: update copyright description
disp: msm: sde: configure dest_scaler op_mode for two independent displays
disp: msm: dp: updated copyright set for 4nm target
Revert "disp: msm: sde: consider max of actual and default prefill lines"
disp: msm: sde: Reset backlight scale when HWC is stopped
disp: msm: dp: avoid duplicate read of link status
disp: msm: dsi: update vreg_ctrl settings for cape
disp: msm: fail commit if drm_gem_obj was found attached to a sec CB
disp: msm: dp: updated register values for 4nm target
disp: msm: sde: update framedata event handling
disp: msm: dsi: Add new phy comaptible string for cape
disp: msm: sde: software override for fal10 in cwb enable
disp: msm: update cleanup during bind failure in msm_drm_component_init
disp: msm: sde: dump user input_fence info on spec fence timeout
disp: msm: sde: add null pointer check for encoder current master
disp: msm: dsi: enable DMA start window scheduling for broadcast commands
disp: msm: sde: avoid alignment checks for linear formats
disp: msm: reset thread priority work on every new run
disp: msm: sde: send power on event for cont. splash
disp: msm: sde: always set CTL_x_UIDLE_ACTIVE register to "1"
disp: msm: use vzalloc for large allocations
disp: msm: sde: Add support to limit DSC size to 10k
disp: msm: sde: add tx wait during DMS for sim panel
disp: msm: dsi: add check for any queued DSI CMDs before clock force update
disp: msm: sde: correct pp block allocation during dcwb dither programming
disp: msm: sde: avoid setting of max vblank count
disp: msm: sde: add cached lut flag in sde plane
disp: msm: sde: avoid use after free in msm_lastclose
disp: msm: sde: update TEAR_SYNC_WRCOUNT register before vsync counter
disp: msm: dsi: Support uncompressed rgb101010 format
disp: msm: sde: update idle_pc_enabled flag for all encoders
disp: msm: sde: flush esd work before disabling the encoder
disp: msm: sde: allow qsync update along with modeset
disp: msm: dp: avoid dp sw reset on disconnect path
disp: msm: sde: consider max of actual and default prefill lines
disp: msm: ensure vbif debugbus not in use is disabled
disp: msm: sde: update cached encoder mask if required
disp: msm: sde: while timing engine enabling poll for active region
disp: msm: enable cache flag for dumb buffer
disp: msm: sde: disable ot limit for cwb
disp: msm: sde: avoid race condition at vm release
disp: msm: dsi: set qsync min fps list length to zero
disp: msm: sde: reset mixers in crtc when ctl datapath switches
disp: msm: sde: update vm state atomic check for non-primary usecases
disp: msm: sde: reset CTL_UIDLE_ACTIVE register only if uidle is disabled
Change-Id: If480e7f33743eb4788549f853ba05e744ecb38d3
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
This change updates copyright description with correct
license marking as per the guidelines.
Change-Id: Ia74b721e78afcc7f8e88bcbccfcf15430111ec37
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
