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Rajkumar Subbiah
4effde5930 disp: msm: dp: check capability before enabling crc
This is a partial revert of I67ace5c064b2b56d03732a78f334ea6b1b649608 which tries
to enable Sink CRC irrespective of the sink's CRC capability to workaround an
issue with a specific sinks which reports incorrect capability on first plugin.
But this causes some MST dongles to misbehave causing one or both outputs to
be blank.

Change-Id: I70c70db8ac371fe0094a45780216a2518d688a36
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
2023-03-20 16:13:09 -04:00
qctecmdr
280c38cc54 Merge "disp: msm: dp: check panel state before accessing dp audio registers" 2023-03-13 21:55:12 -07:00
qctecmdr
de9bb5b29c Merge "disp: msm: dp: skip crc read if pclk is not on" 2023-03-13 21:55:12 -07:00
qctecmdr
031728b5c6 Merge "disp: msm: dp: create dp aux log ipc context at probe time" 2023-03-13 21:55:12 -07:00
Nisarg Bhavsar
65925ebbf0 disp: msm: dp: check panel state before accessing dp audio registers
During DP disable, it is possible for audio and display to race
causing the audio to send teardown notification after display driver
has disabled all the clocks. This change adds a check for panel state to
avoid accessing registers during this callback.

Change-Id: I6322726a04745bc6c73338cd33f65cfdbfe42ec7
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
2023-03-08 06:58:32 -08:00
Nisarg Bhavsar
1948a72655 disp: msm: dp: force max bpp to 24 for MST
Force max supported bpp to 24 to improve stability of MST usecases.

Change-Id: I5b0e6ad86df39915073f469ea67e6addea165965
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
2023-03-07 19:12:44 -05:00
Rajkumar Subbiah
da304b72c6 disp: msm: dp: skip crc read if pclk is not on
The DP debugfs node for CRC read currently does not check
if the panel is enabled before attempting the read. This
could cause unclocked access of DP registers. This change
adds the necessary protection and bails out if the clocks
are not turned on.

Change-Id: Ia555e2473fc9f0f7434ee3665eb4fb7cfb4f97cf
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
2023-03-06 21:16:01 -05:00
Rajkumar Subbiah
ae1ea3d993 disp: msm: dp: create dp aux log ipc context at probe time
Currently the ipc context for drm_dp_aux is being created
during dp_aux_init. This limits the IPC logs to be only
readable when the external display is in connected state
and it gets destroyed on unplug. This change moves the
context creation to probe time and the aux context will
be passed to the aux driver during initialization.

Change-Id: Id8d26c907c9cb2fd8c89b2842b98e7a908816abe
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
2023-03-06 18:12:50 -08:00
Rajkumar Subbiah
23955331e6 disp: msm: dp: add marker to dp aux error logs
Some rate limited logs in dp aux and dp ctrl are using
pr_err_ratelimited function to print the logs instead of
the standard DP log macros. So this change adds a new
ratelimited DP log macro and make the logging consistent.

Change-Id: I75d7306d94c7c360783f39259c509c32fe59cdf5
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
2023-03-06 18:10:54 -08:00
Rajkumar Subbiah
7ac494a18e disp: msm: dp: reenable sink crc for robustness
Some monitors seem to be not enabling Sink CRC capability on first plugin
and therefore the CRC read returns all zeros. But on subsequent plugins
the capability is set properly and CRC values are calculated. To
workaround this quirk on the sink side, this change reenables sink CRC
if the values are read as zeros.

Change-Id: I67ace5c064b2b56d03732a78f334ea6b1b649608
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
2023-02-28 16:24:47 -08:00
Nisarg Bhavsar
548dc93b0e disp: msm: dp: update resource tracking for 8k@30
Update tracking of layer mixer resources to prevent valid modes
from being skipped during DP topology validation.

Change-Id: Id88337094c4113b721f307d24583a3ca30157216
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
2023-02-21 08:15:50 -08:00
qctecmdr
990fc93293 Merge "disp: msm: dp: modify hdcp wait loop to not add to cpu load" 2023-02-17 07:13:26 -08:00
Andrew Bartfeld
c7d1996e90 disp: msm: dp: modify hdcp wait loop to not add to cpu load
Currently, hdcp wait loops uses the wait_event() macro which sets the
status of the thread to WAIT_UNINTERRUPTIBLE and contributes to system
load. The macro wait_event_idle() polls for a changing condition in the
same way but instead sets the thread status to WAIT_IDLE which does not
contribute to system load. This prevents hdcp threads from appearing as
hung threads in system load summaries while still properly polling for
status changes.

Change-Id: Ie6991881d912ba6fca6bb0fd9558633b1fb83492
Signed-off-by: Andrew Bartfeld <quic_abartfel@quicinc.com>
2023-02-10 13:05:48 -08:00
qctecmdr
fbf774bf9b Merge "disp: msm: dp: port API changes related to MST payload update" 2023-01-29 22:32:25 -08:00
Sandeep Gangadharaiah
51ee816c56 disp: msm: dp: port API changes related to MST payload update
Latest LTS kernel has refactored the payload code for MST. This
change port the latest payload related API changes.

LINKED: https://patchwork.freedesktop.org/patch/498176/
Change-Id: I0f5bfe30824c5a9bbf4bc346a24f236a53bc0d70
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
2023-01-26 12:57:47 -08:00
qctecmdr
99172cbda2 Merge "disp: msm: dp: enable data flow related interrupts" 2023-01-06 12:29:56 -08:00
Rajkumar Subbiah
0b72b0d810 disp: msm: dp: add debugfs node for bpp override
Add a debugfs node to set maximum bpp for the base panel which will
be used in both SST and MST use cases to limit the bpp.

Change-Id: I0ef7866e2b82a2078d6cdf97ee0d7226c2125b21
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
2023-01-05 07:19:13 -08:00
Rajkumar Subbiah
6c0776936e disp: msm: dp: enable data flow related interrupts
Enable interrupts to monitor SST/MST data flow related notifications
from hw.

Change-Id: I28ffc7af1445fdb48f38b11974a05bf84f7e6bc7
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
Signed-off-by: Rajkumar Subbiah <rsubbia@codeaurora.org>
2023-01-05 07:19:00 -08:00
Sandeep Gangadharaiah
d35438d1be disp: msm: dp: reorder update payload call during slot calculation
Currently get vcpi info call is returning wrong slot info since update
payload function is called afterwards. The latter function is calculating
the slot info which is read back by get vcpi call. This change reorders
these function calls. Also, this change sets start_slot to be always 1.
This is the value expected by upstream driver for atomic drivers.
This is a follow up change for the commit 19a9abf064
("disp: msm: dp: update MST first link slot information").

Change-Id: I620125a2d73afb7537a3540ee129e2a4eb0c488c
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
2022-12-05 13:13:42 -08:00
Sandeep Gangadharaiah
b96376cfd1 disp: msm: dp: fix vco rate calcuation for stream clocks
This change fixes the incorrect calculation of VCO rate for
stream clocks. This issue was introduced because of a previous
commit e4e277ad36 ("disp: msm: dp: Convert clock operations to byte2 ops").

Change-Id: I2886f98a95fd7c166edabec3fc023dc9846c201d
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
2022-11-21 07:03:23 -08:00
qctecmdr
f08f714919 Merge "disp: msm: dp: fix bpp to 24 in TU calc for SST DSC" 2022-11-13 09:31:20 -08:00
Rajkumar Subbiah
2238b58cf0 disp: msm: dp: fix bpp to 24 in TU calc for SST DSC
When using the TU calculator for SST DSC usecase, the calculator
expects the bpp to be 24 irrespective of the actual panel bpp.

Change-Id: Ifdab2c00a2a99b4d7d7dea7eadb33bc34e3cfa8b
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
2022-11-13 02:53:19 -08:00
Rajkumar Subbiah
dd369b2bdb disp: msm: dp: use compressed bpp for RG calculation
When calculating the Rate Governor parameters for MST, if the
stream is compressed, the calculator expects the input bpp to be
the compressed bpp, but currently the driver is passing uncompressed
bpp. This change updates the driver to pass compressed bpp to the
calculator.

Change-Id: Iac51d75843bd0072bbe07142ac4533d841f795f5
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
2022-11-13 02:53:07 -08:00
qctecmdr
f62878f3ab Merge "disp: msm: dp: Add abstract and wcd939x aux switch support" 2022-11-03 19:18:25 -07:00
Nisarg Bhavsar
4a2e5b3fe1 disp: msm: dp: Add abstract and wcd939x aux switch support
Add functionality to change which aux switch is used
at compile time for different targets. Add wcd939x
switch support.

Change-Id: Iced3b11733009680063790dfa8f180b19002f963
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
2022-11-01 19:15:01 -07:00
Andrew Bartfeld
5dcee7c010 disp: msm: dp: avoid releasing vcpi for active crtc
In MST atomic check function, add a check to ensure it's a disable call
before releasing vcpi slots to ensure atomic_release_vcpi_slots() and
atomic_find_vcpi_slots() are never called in the same atomic check
as mentioned in the kernel docs.

Change-Id: I36cf689b4d3bf9d2469a6c402b6377a667f01c12
Signed-off-by: Andrew Bartfeld <quic_abartfel@quicinc.com>
2022-11-01 05:27:16 -07:00
Sandeep Gangadharaiah
c76df5605c disp: msm: dp: enable aux switch from display HPD handler
Currently, aux switch is enabled by usbpd handler before
handing over the control to dispaly HPD handler. However,
in some scenarios there is a chance that altmode would
directly call into display HPD handler bypassing the usbpd
handler. This would lead to aux errors since aux switch
is not enabled. This change will enable aux switch in
display HPD handler which would avoid the resulting aux
errors. This issue is a regression caused by this change
b6466ca7f597396cd2ecb3623d059435dfb0e4c6.

Change-Id: I425991ba95b22411740f88cba5ca2083d13969e1
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
2022-10-29 16:23:35 -07:00
qctecmdr
354c9c0b46 Merge "disp: msm: dp: Convert clock operations to byte2 ops" 2022-10-28 08:05:48 -07:00
Sandeep Gangadharaiah
e4e277ad36 disp: msm: dp: Convert clock operations to byte2 ops
Convert clock operation to byte2 ops to meet DISPCC requirement.
Clock unit is changed from KHZ to HZ. Added link clock parent as
freq table is no longer supported in byte2 ops.

Change-Id: Icf5a595708040e8afefecebe7f371bb832d6673e
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
2022-10-27 15:39:14 -07:00
GG Hou
19a9abf064 disp: msm: dp: update MST first link slot information
update MST first link slot information as upsteam interface

Link: https://patchwork.freedesktop.org/patch/msgid/20211025223825.301703-3-lyude@redhat.com

Change-Id: I871504942d596ee742e5481be9c8b6cf0f50e8ac
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
2022-10-26 14:11:37 -04:00
GG Hou
11f0929a72 disp: msm: dp: update include file path for upstream headers
This change updates the include file path for necessary dp
and dsc headers that have moved in upstream kernel.

File path changed in upstream:
include/drm/display/drm_dp_aux_bus.h
include/drm/display/drm_dp_dual_mode_helper.h
include/drm/display/drm_dp.h
include/drm/display/drm_dp_helper.h
include/drm/display/drm_dp_mst_helper.h
include/drm/display/drm_dsc.h
include/drm/display/drm_dsc_helper.h
include/drm/display/drm_hdcp.h
include/drm/display/drm_hdcp_helper.h
include/drm/display/drm_hdmi_helper.h
include/drm/display/drm_scdc.h
include/drm/display/drm_scdc_helper.h

Change-Id: Icb9a227c7464061f68fe60cbda6d93858fa768c5
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
2022-10-10 11:06:29 -07:00
Linux Build Service Account
78456d91bb Merge "disp: msm: dp: disable aux switch at the start of the disconnect path" into display-kernel.lnx.1.0 2022-09-23 12:20:25 -07:00
Sandeep Gangadharaiah
cc997cd3d1 disp: msm: dp: disable aux switch at the start of the disconnect path
Currently the aux switch is disabled at the end of the disconnect
path which would include the wait time upto 5 secs becauase of usermode
cleanup. However, the PMIC module is expecting the aux switch to be
disabled within 400 msec after the disconnect is notified. If not, this
would trigger an LPD failure. This change moves aux switch disable
further up in the disconnect path, before waiting on completion of
usermode cleanup.

Change-Id: I42e0608f06127729a78de11631d16d0a3ca0d2b4
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
2022-09-23 11:48:47 -07:00
Sandeep Gangadharaiah
31ae12f079 disp: msm: dp: clear MST sim context during DP sim disable
After freeing MST sim context memory the pointer isn't set
to NULL leading to unauthorized memory access. Along with
this fix, this change also defers checking sim device ports
pointer at a more appropriate place in the function call.

Change-Id: I20c09edbd454c9d491060815dc73bae34aab6b08
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
2022-09-23 11:48:28 -07:00
qctecmdr
df56ac358f Merge "disp: msm: dp: resend hpd notification to usermode" 2022-08-31 07:46:50 -07:00
Rajkumar Subbiah
ecaabfefc9 disp: msm: dp: resend hpd notification to usermode
This change adds robustness to hpd notification by resending
it if there was no action in 2 seconds, just in case, the
first notification didn't make it to the usermode.

Change-Id: Iaf00669ec77e8c50618ee5618735a98518ad7f1a
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
2022-08-30 13:45:59 -07:00
Rajkumar Subbiah
5043291e1a disp: msm: dp: skip waits when processing usb disconnect in sim mode
With real DP over Type-C sinks, DP driver requests access to USB
combo PHY from USB driver. But in DP SIM mode, there is no real
sink and PD management, so the combo PHY is managed by USB driver
and DP driver uses it without actually claiming it. If the USB
cable is unplugged in this scenario, USB driver notifies the
disconnection through an atomic notifier call. It does not expect
the handler to go into sleep, but the disconnect handler inside
DP driver has multiple wait for events and also sleeps to wait for
HW state updates.

This change passes a skip_wait flag to all the disable functions
to complete disconnect processing by skipping all processor sleeps
and event waits.

Change-Id: Ia98de0e7fa6b0573e644615ee59015914a93f4cf
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
2022-08-30 13:43:49 -07:00
Sandeep Gangadharaiah
2e9d68e174 disp: msm: dp: free DP sim ports during DP sim disable
DP sim ports created during DP sim enable aren't cleared
during disable path. This would retain the last status of
the DP sim port or the connector. This would impact the
next iteration of DP sim test, if done without device
reset. This change will set the port number to 0 during
DP sim disable and clear the memory allocated for these
ports.

Change-Id: I386a62e87fcaf006db8dd18e5751b33bbe70fc9b
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
2022-08-30 10:27:45 -07:00
Rajkumar Subbiah
7eef92843d disp: msm: dp: add debug node to capture source and sink crc
This change adds a debug node named 'crc' to drm_dp to read
the frame CRC values for DP controller and DP Sink. In order
to facilitate the immediate read of the CRC values when
accessed, it enables the CRC calculation on the controller
and sink automatically when the stream is enabled. In addition
to the frame CRC values it also reads the MISR values from
controller and PHY to validate the data flow from controller
to PHY.

Change-Id: I1acee2dba931e4635caf4a400e336a72c86e88bf
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
2022-08-24 13:47:27 -07:00
qctecmdr
c037ed6b7c Merge "disp: msm: dp: remove register call for regdump framework for DP domains" 2022-08-17 18:44:04 -07:00
qctecmdr
8ac778f8e1 Merge "disp: msm: dp: remove disconnect call for downstream port status change" 2022-08-12 16:02:35 -07:00
Sandeep Gangadharaiah
e60e9026fc disp: msm: dp: remove register call for regdump framework for DP domains
Currently regdump framework for all the DP domains are registered during
init. But, unlike other modules in DP each SWI module is controlled by
its own clock and cannot be read without turning on the corresponding
clocks. Trying to do so might lead to unexpected behavior. This change
removes registering these nodes.

Change-Id: Ib20d7212bde24f3858558009e1679661731d16df
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
2022-08-10 11:29:19 -07:00
qctecmdr
5a5adbba9f Merge "disp: msm: dp: address race condition in LM allocation" 2022-08-09 20:49:21 -07:00
Sandeep Gangadharaiah
f86e196de0 disp: msm: dp: remove disconnect call for downstream port status change
During MST scenario, plugging out all the downstream monitors connected
to the MST hub would trigger a disconnect handler which would cleanup
display structure. This isn't required since MST hub is still connected
and the display cleanup would be taken care during the actual MST hub
disconnect. Also, handling the disconnect immediately on port status
notification leaves the usermode in an invalid state where it assumes
the display is still enabled and results in commit errors.

Change-Id: Ia9a58fadd89bd05746da25f142b54b31e8567258
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
2022-08-09 11:28:01 -07:00
Sandeep Gangadharaiah
0763e33723 disp: msm: dp: fix aux state during individual plug out/in
When a display is powered off, the DP driver currently clears the aux
state and forces it to OFF, expecting a subsequent hpd_low. But in MST
scenarios it is possible for individual displays to be unplugged and then
plugged back in without disconnecting the hub. In this use case, after
the unplug of last display, the aux state is in OFF, and on the
subsequent plug-in, the driver appends the ON flag, leaving both flags
to be set which is an incorrect state. This change removes this
assumption and properly sets the ON/OFF state on enable/disable
respectively.

Change-Id: I96355938a14c77fe958b86bd5f1dabad67584e4e
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
2022-08-03 20:33:56 -07:00
Vara Reddy
df69a7d379 disp: msm: dp: destroy audio workqueue outside session_lock
Change moves destroying dp audio workqueue outside dp session_lock.
As part of disconnect, USB driver uses atomic notifier which holds
rcu_read_lock and calls into DP disconnect callback which needs
session_lock. If another DP threads holds DP session_lock then
we block RCU operations.

Change-Id: I5d565ca149a3a34ebd5ede4fb662982d87454f16
Signed-off-by: Vara Reddy <quic_varar@quicinc.com>
2022-07-29 16:19:42 -07:00
qctecmdr
66a9a093e7 Merge "disp: msm: dp: set DSC capabilities in mode only if panel supports DSC" 2022-07-28 21:43:58 -07:00
qctecmdr
601b7c8c96 Merge "disp: msm: dp: update DP aux state with correct status" 2022-07-28 21:43:58 -07:00
Sandeep Gangadharaiah
24d4662c83 disp: msm: dp: set DSC capabilities in mode only if panel supports DSC
During mode validation, DSC book-keeping logic is executed irrespective
of the panel DSC status. If the DSC blocks are available then the
corresponding mode is also set as DSC capable. This step is uncalled for
in a non-DSC panel scenario and might lead to unexpected behavior. This
change checks for panel DSC status before updating DSC book-keeping and
capability for the mode.

Change-Id: I30d6a4d7f3e772b7b13fcca6e318e96372a8becb
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
2022-07-27 12:27:03 -07:00
Sandeep Gangadharaiah
603ae09669 disp: msm: dp: update DP aux state with correct status
End section of the display post enable which is supposed
to do the cleanup before exit is also setting DP aux state
as powered on and notifying the connect as successful.
If there is a race condition between connect and disconnect
paths then the code execution would skip to the end section
since display is already disabled. In this case, the DP aux
state would be misleading. This change will set the status
and notify complete only during success case.

Change-Id: I1eca511e042d2dea619bf85fcc28adf9e0cc9536
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
2022-07-26 21:15:48 -07:00