Lane enable register reset is not required any delay to reflect the
change. This change removes the unnecesaary delay from lane_enable
register. Also, adding 1us of delay between back to back write in
SW reset register along with condition based refelction of delay.
CRs-Fixed: 2671221
Change-Id: I010570045a97fc1489a84d22ebd39df6f6f14f0a
Signed-off-by: Jigarkumar Zala <jzala@codeaurora.org>
Update 2phase and 3phase bring up sequence for different
data rate to reflect latest hpg change.
CRs-Fixed: 2671221
Change-Id: Idd7445a523486a5fb4ec5d43bcf8987c54c089b0
Signed-off-by: Jigarkumar Zala <jzala@codeaurora.org>
To simulate bus overflow recovery in camera, cpas needs sysfs
to take input from shell and vote the final value as given,
instead of consolidated values from cpas clients. Add initial
support for sysfs to add nodes for all drivers. Add sysfs
based debug node to maintain and update all settings. Add cpas
settings to override final bw voted to camnoc and mnoc ports.
Usage:
adb shell "echo <driver_name>#<setting_name>=<value>
> /sys/devices/platform/soc/soc:qcom,cam-req-mgr/debug_node"
Example:i
adb shell "echo cpas#camnoc_bw=100
> /sys/devices/platform/soc/soc:qcom,cam-req-mgr/debug_node"
Input format for updating settings is strict.
CRs-Fixed: 2646825
Change-Id: I8d6063240f9685474bf4b2899e8dfb3f74cbdb75
Signed-off-by: Mukund Madhusudan Atre <matre@codeaurora.org>
During global reset, csi rx irq bits are set since sensor/phy was not
reset properly in last closure and sending some data. This can lead
to csid fatal or non-fatal errors.
To avoid this condition, ignore other csid irq errors during csid top
reset and during csid stop sequence.
CRs-Fixed: 2585726
Change-Id: I5e09caf3b374407ece8ff1b871c2cf7e0f1837ac
Signed-off-by: Chandan Kumar Jha <cjha@codeaurora.org>
Signed-off-by: Depeng Shao <depengs@codeaurora.org>
Signed-off-by: Vishalsingh Hajeri <vhajeri@codeaurora.org>
Currently the ahb clock rate is set as part of cpas_start for a
given client. In order to set this rate, any camera gdsc needs to
be enabled. This change adds a check to allow setting the clk rate
only if the gdsc regulator has been enabled to avoid NoC timeouts.
CRs-Fixed: 2671048
Change-Id: I6551c8c648ae298dca97f0e35ba7c9ca83b5a2cd
Signed-off-by: Karthik Anantha Ram <kartanan@codeaurora.org>
In dual ife usecase we get two cdm callbacks from respective
internal cdm's. This change makes sure per req reg dump function
is called only once when two cdm callbacks are received.
CRs-Fixed: 2666317
Change-Id: I766dbe471cbee0fd2d26e7618ebc06a9f185a873
Signed-off-by: Vishalsingh Hajeri <vhajeri@codeaurora.org>
In many error cases it is required to know the
bandwidth applied on axi ports and camnoc axi
clock rate values. Added cpas api to print the
current axi bus votes, camnoc axi clock and ahb
vote level.This api can be called for isp errors
such as bus overflow, pxl overflow cases.
On RDI overflow printing last applied IFE clock,
dumping the CAMNOC fill-level registers to know
the pending and queued transactions, SOF EPOCH
and EOF timing to know exactly at what time the
RDI overflow came, Width and height of specific
Write master.
CRs-Fixed: 2623885
Change-Id: I92a9097efe9f6726748ec27ca39dd51c8c6de1b6
Signed-off-by: Mukund Madhusudan Atre <matre@codeaurora.org>
Do not compile camera sources for VM image for lahaina.
Guard the source path against CONFIG_QTI_VM to decide to
compile it are not.
CRs-Fixed: 2663712
Change-Id: I4a624cf8d9824b545c8fb70c134a3b7011c4d2ca
Signed-off-by: Vishalsingh Hajeri <vhajeri@codeaurora.org>
Static variables are initialized only once and the compiler
persists with the variable till the end of the program hence
declaring some of the varaibles in header files as static.
CRs-Fixed: 2663712
Change-Id: I55265f5ac1d144ae5b5c62a9984c08d242be157d
Signed-off-by: Vishalsingh Hajeri <vhajeri@codeaurora.org>
Secure CP control register always assume that it contains 7 bit
mask for each PHY. But this register format is different based on
target. Update secure CP control bitmask generation logic for each
PHY index based on phy_version.
So we have below 3 combinations to handle at SW.
1.Old Titan Targets : 7 bits for each PHY.
2.PHY 1_2_1 : for 4 pHYS 7 bits and for
remaining 2 PHYs 8 bits are reserved.
3.Mimas (PHY 2_0_1): 8 bits for each PHY.
CRs-Fixed: 2624698
Change-Id: Iac4c3c718fc96a51592e07b45458fb045c52366d
Signed-off-by: Anil Kumar Kanakanti <akanakan@codeaurora.org>
Auto clock gating was disabled to aid in certain debug scenarios.
However, for normal operation the expectation is for auto clock
gating to be enabled. The writes could be removed as enabled is the
default, but no harm in being explicit.
CRs-Fixed: 2584631
Change-Id: I63336d12b94f270c4962281e14e879a6207ea386
Signed-off-by: Fernando Pacheco <fpacheco@codeaurora.org>
There is a possibility that the priority variable would be
accessed even for the HEAD node which would result in
out of bound errors, so access the elements of the
structure only if the handler is found.
CRs-Fixed: 2646173
Change-Id: I0540658b9c9487f6e3a4601a488a1add1e790dda
Signed-off-by: Tejas Prajapati <tpraja@codeaurora.org>
For some cpas clients like csiphy, cci voting is applied and
removed during their respective start and stop flow. Such
clients do no call for vote update explicitly.
For such cases, camnoc axi ports were not updated. This can
result in camnoc_sf vote to be present.
This commit updates the camnoc ports as well for the clients
for who the voting is applied and removed during the start and
stop only.
CRs-Fixed: 2571273
Change-Id: I2997e5abad904532dc0d582edbf6d6078ac732d7
Signed-off-by: Gaurav Jindal <gjindal@codeaurora.org>
For link with maximum pipeline delay of 1 e.g.,
TPG use case or sensors with pipeline delay of 1,
if the request is not submitted before 2
consecutive triggers we do not get chance to
increment rd idx, in the mean time the slot which
was last applied will be reset and we will not be
able to apply request even if new requests are scheduled.
This will cause the camera to not apply any request
further, hence increasing the rd idx if no lower pd
devices are pending will fix the issue.
CRs-Fixed: 2622845
Change-Id: I012e242c7fca22abecc171ef4d7063d851bb5748
Signed-off-by: Tejas Prajapati <tpraja@codeaurora.org>
For lagoon, few changes in CSID and IFE to handle the
dual vfe sync and halt.
For CSID, while handling the halt, external and internal
core configuration is changed.
For VFE, 3 IFE support is possible with the combinations:
0-1, 1-2, 0-2. This requires changes in dual vfe sync handling.
Also, CSID and IFE versions are updated.
This commit adds the driver header files for the version and
handles the hardware changes in the driver.
CRs-Fixed: 2571273
Change-Id: I48fd3319692cc1044beb20c278cc2fe5676cb668
Signed-off-by: Gaurav Jindal <gjindal@codeaurora.org>
Signed-off-by: Vishalsingh Hajeri <vhajeri@codeaurora.org>
New usecase for flash driver requires to be trigger at EOF.
This change adds the new operation code support in flash
driver along with EOF enable support in crm and across
other drivers. Also to improve the performance, this change
adds the logic to dynamically update the subscribe event to
CRM, so that CRM can enqueue EOF events when Flash or any other
device add the request for EOF.
CRs-Fixed: 2633194
Change-Id: I2f68ac7fc6a4699debd39b64319728cdf17bbcfa
Signed-off-by: Jigarkumar Zala <jzala@codeaurora.org>
During apply vote axi port name is coming as null. Add
missing axi port name info in cpas layer also for more
descriptive log during apply.
CRs-Fixed: 2584631
Change-Id: Ibf99b542101a39c415157797e36b5605962873cb
Signed-off-by: Mukund Madhusudan Atre <matre@codeaurora.org>
Add trace events for IRQ's on IFE top side and IFE
BUS side in top half. These traces when enabled
will help to gather relative timing information of
the IRQ's with systrace.
CRs-Fixed: 2538876
Change-Id: I856a9df1978f90e260da7c62cadf02fa2fe53202
Signed-off-by: Vishalsingh Hajeri <vhajeri@codeaurora.org>
Signed-off-by: Pavan Kumar Chilamkurthi <pchilamk@codeaurora.org>
