提交線圖

3181 次程式碼提交

作者 SHA1 備註 日期
qctecmdr
4bb0038c6b Merge "disp: msm: sde: bound event log traversal to allocated memory in coredump" 2022-08-17 18:44:05 -07:00
qctecmdr
1c8167f09f Merge "disp: msm: sde: add crtc width restriction when 3d-merge is enabled" 2022-08-17 18:44:04 -07:00
qctecmdr
c037ed6b7c Merge "disp: msm: dp: remove register call for regdump framework for DP domains" 2022-08-17 18:44:04 -07:00
Amine Najahi
8a4d70c9ca disp: msm: sde: bound event log traversal to allocated memory in coredump
Currently, driver is determining the amount of memory to allocate
based on the event log object indexes (first, last). The last index
can change if there is additional logging done during the coredump
phase and potentially cause an out-of-bound memory access during
buffer traversal.

This change restrict the event log object traversal to a maximum
of the output buffer size.

Change-Id: I91e5734362d2d7a796129fce85e27611bab2245f
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
2022-08-17 15:29:20 -04:00
qctecmdr
d273ee1f5e Merge "disp: msm: sde: disable spr and demura for secondary panel in trusted vm" 2022-08-17 12:04:50 -07:00
Veera Sundaram Sankaran
3550ca8f9f disp: msm: sde: add crtc width restriction when 3d-merge is enabled
Add validation during crtc_atomic_check to have crtc width as
multiple of 4 when dualpipe 3d-mux is enabled and multiple of 8
when quadpipe 3d-mux is enabled. This ensures each layer mixer
is having an even width.

Change-Id: I5dc173c1b0349430a8e12a7b1c9440c7854e7ecd
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2022-08-16 18:44:17 -07:00
qctecmdr
50420e8d17 Merge "disp: msm: sde: convert ubwc stats roi into blob property" 2022-08-14 00:30:30 -07:00
qctecmdr
c525494531 Merge "disp: msm: dsi: increase cmd dma timeout to 1200 milliseconds" 2022-08-13 17:38:10 -07:00
qctecmdr
8ac778f8e1 Merge "disp: msm: dp: remove disconnect call for downstream port status change" 2022-08-12 16:02:35 -07:00
qctecmdr
df6829fdf3 Merge "disp: msm: sde: add check to avoid NULL WB output fb" 2022-08-12 16:02:34 -07:00
Vara Reddy
3d82106dee disp: msm: dsi: increase cmd dma timeout to 1200 milliseconds
Change increases cmd dma timeout to 1200 milliseconds from 200 milliseconds.
There are video mode panels which can support one frame per second, if pixel
data transfer is active, then our command transfer timeout should be atleast
1000 msec.

Change-Id: I3e8269febe3ed6e55ac9381a8de35e7d19fa3160
Signed-off-by: Vara Reddy <quic_varar@quicinc.com>
2022-08-12 09:51:55 -07:00
Nilaan Gunabalachandran
eab3fd66db disp: msm: sde: convert ubwc stats roi into blob property
This change converts the ubwc stats roi into a blob property. This
allows for the roi data structure to be passed into kernel.

Change-Id: I4b30dcc16bcbd152428861444ff321add860942f
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
2022-08-11 11:45:14 -07:00
Veera Sundaram Sankaran
5196a85f67 disp: msm: sde: update hw configs on dnsc_blur disable
Currently, dnsc_blur hardware block is not updated when the connector
dnsc_blur property is set to NULL or when dnsc_blur_count is 0. Update
the dnsc_blur hw block configs to avoid stale configs affecting the
current frame.

Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Change-Id: If64dc5548b03edba401fb7f40edf3419dbe57ca3
2022-08-10 12:30:45 -07:00
Veera Sundaram Sankaran
d65c12ca5a disp: msm: sde: add check to avoid NULL WB output fb
Change the debug message to error during the writeback
encoder validate for wb output buffer. The output buffer
can be NULL only during disable frame and all other frames
need to have a valid output buffer.

Change-Id: I4d6fecfeaf863e56fe25e17ab1200849003b3309
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2022-08-10 11:38:31 -07:00
Sandeep Gangadharaiah
e60e9026fc disp: msm: dp: remove register call for regdump framework for DP domains
Currently regdump framework for all the DP domains are registered during
init. But, unlike other modules in DP each SWI module is controlled by
its own clock and cannot be read without turning on the corresponding
clocks. Trying to do so might lead to unexpected behavior. This change
removes registering these nodes.

Change-Id: Ib20d7212bde24f3858558009e1679661731d16df
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
2022-08-10 11:29:19 -07:00
qctecmdr
5a5adbba9f Merge "disp: msm: dp: address race condition in LM allocation" 2022-08-09 20:49:21 -07:00
Alisha Thapaliya
046b2d1e35 disp: msm: sde: disable spr and demura for secondary panel in trusted vm
When spr and demura init config function pointers are not null,
then only enable those features. For secondary panel in dual display
for trusted ui, these features will be disabled.

Change-Id: Idcbc672d9da62664bdbaa9489dbfac9f6ab80ec1
Signed-off-by: Alisha Thapaliya <quic_athapali@quicinc.com>
2022-08-09 13:08:01 -07:00
Sandeep Gangadharaiah
f86e196de0 disp: msm: dp: remove disconnect call for downstream port status change
During MST scenario, plugging out all the downstream monitors connected
to the MST hub would trigger a disconnect handler which would cleanup
display structure. This isn't required since MST hub is still connected
and the display cleanup would be taken care during the actual MST hub
disconnect. Also, handling the disconnect immediately on port status
notification leaves the usermode in an invalid state where it assumes
the display is still enabled and results in commit errors.

Change-Id: Ia9a58fadd89bd05746da25f142b54b31e8567258
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
2022-08-09 11:28:01 -07:00
qctecmdr
e540ee198b Merge "disp: msm: sde: enable encoder resources before phys enc disable" 2022-08-08 20:01:57 -07:00
qctecmdr
88df673d58 Merge "disp: msm: sde: reduce stack size in _sde_crtc_check_rois" 2022-08-08 20:01:57 -07:00
Amine Najahi
18d42a6eb3 disp: msm: sde: use mode from new state during CP check phase
Currently previous mode information is passed to CP check phase
instead of the new incoming mode, which cause RC to silently
pass the check phase when there is a resolution mismatch between
the RC mask and new mode.

This change also adds various event log to better track RC codeflow.

Change-Id: I8953fd76e2cb0eb12e2df23038a7866edd3dcb1e
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
2022-08-08 13:31:12 -04:00
Veera Sundaram Sankaran
965ac39c84 disp: msm: sde: enable encoder resources before phys enc disable
Enable the clks/irqs & update RSC state during encoder disable.
This ensures RSC is in correct state during the non-primary disable
commit as it might have entered idle power collapse before the
disable.

Change-Id: Idf82efb3a7bc895e1a97c6cdeeb62970184c8e5d
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2022-08-08 10:15:11 -07:00
qctecmdr
771d2ae78d Merge "disp: msm: sde: Add scaler offset for de lpf" 2022-08-07 20:39:14 -07:00
qctecmdr
cf9129e168 Merge "disp: msm: dp: fix aux state during individual plug out/in" 2022-08-06 03:04:57 -07:00
qctecmdr
adde40d0a0 Merge "disp: msm: dsi: Enable TPG functionality" 2022-08-06 03:04:57 -07:00
Sandeep Gangadharaiah
0763e33723 disp: msm: dp: fix aux state during individual plug out/in
When a display is powered off, the DP driver currently clears the aux
state and forces it to OFF, expecting a subsequent hpd_low. But in MST
scenarios it is possible for individual displays to be unplugged and then
plugged back in without disconnecting the hub. In this use case, after
the unplug of last display, the aux state is in OFF, and on the
subsequent plug-in, the driver appends the ON flag, leaving both flags
to be set which is an incorrect state. This change removes this
assumption and properly sets the ON/OFF state on enable/disable
respectively.

Change-Id: I96355938a14c77fe958b86bd5f1dabad67584e4e
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
2022-08-03 20:33:56 -07:00
Renchao Liu
fcaf279afd disp: msm: sde: Add scaler offset for de lpf
Scaler offset is missed while writing de lpf register,
which may cause DE works mainly on the left part of panel.
this change adds the offset to fix this issue.

Change-Id: I7cdc3afd3523cb9e15a7ae79adae07e2b52b8c2e
Signed-off-by: Renchao Liu <quic_rencliu@quicinc.com>
2022-08-04 10:10:50 +08:00
Nisarg Bhavsar
5e0d93196b disp: msm: dsi: Enable TPG functionality
Allow TPG patterns to be displayed on command mode and
video mode panels.

Change-Id: Ie9ba9b404ceb965f8a06d1f19e932dd2e051983b
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
2022-08-03 15:04:54 -07:00
Veera Sundaram Sankaran
ac427feb9e disp: msm: sde: reduce stack size in _sde_crtc_check_rois
Use pointer and allocate dynamic memory for msm_mode_info
in _sde_crtc_check_rois instead of object to reduce the
stack memory size.

Change-Id: Ida8fc7e2b94e19b3c791dcda55a465a4107ef976
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Signed-off-by: Jeykumar Sankaran <quic_jeykumar@quicinc.com>
2022-08-03 14:27:06 -07:00
Srihitha Tangudu
9857e36ddb disp: msm: dsi: Avoid re-initializing PLL registers during dyn clk switch
Currently we are always initializing PLL registers whenever PLL is
configured. Re-initializing PLL registers during dynamic clock switch in
case of cphy video mode is moving the PLL to some bad state resulting in
display freeze. Avoid this by restricting initialization of PLL registers
to only while turning on the PLL.

Change-Id: I09eacbb37fff4e0e91d226ac08e7d5a2bfbbfe26
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
2022-08-03 00:46:15 -07:00
qctecmdr
0034e30af1 Merge "disp: msm: sde: reset wb output crop during cwb disable" 2022-08-02 15:53:49 -07:00
Veera Sundaram Sankaran
e972b51d5c disp: msm: sde: reset wb output crop during cwb disable
Reset the wb crop configs from hardware, while disabling
concurrent writeback. This avoids stale configs which
affects the subsequent writeback session.

Change-Id: I4927effd0650bcdca2852a5d72c3e5478683a90f
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2022-08-01 15:17:05 -07:00
Vara Reddy
df69a7d379 disp: msm: dp: destroy audio workqueue outside session_lock
Change moves destroying dp audio workqueue outside dp session_lock.
As part of disconnect, USB driver uses atomic notifier which holds
rcu_read_lock and calls into DP disconnect callback which needs
session_lock. If another DP threads holds DP session_lock then
we block RCU operations.

Change-Id: I5d565ca149a3a34ebd5ede4fb662982d87454f16
Signed-off-by: Vara Reddy <quic_varar@quicinc.com>
2022-07-29 16:19:42 -07:00
qctecmdr
fd732177c1 Merge "disp: msm: sde: disable hw-fencing for commit before vm transition" 2022-07-28 21:43:58 -07:00
qctecmdr
66a9a093e7 Merge "disp: msm: dp: set DSC capabilities in mode only if panel supports DSC" 2022-07-28 21:43:58 -07:00
qctecmdr
601b7c8c96 Merge "disp: msm: dp: update DP aux state with correct status" 2022-07-28 21:43:58 -07:00
qctecmdr
7045305bcf Merge "disp: msm: dp: update debug message for mst conn id debug node" 2022-07-28 21:43:58 -07:00
Christina Oliveira
b4a071ae7f disp: msm: sde: disable hw-fencing for commit before vm transition
This change disables hw-fencing for the last commit before
vm transition. This avoids configuration issues if hw-fencing is
disabled in the incoming VM.

Change-Id: I573b7d1665f8cef442168bd0ab83a4b2b6cebbb6
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
2022-07-28 13:18:23 -07:00
Sandeep Gangadharaiah
24d4662c83 disp: msm: dp: set DSC capabilities in mode only if panel supports DSC
During mode validation, DSC book-keeping logic is executed irrespective
of the panel DSC status. If the DSC blocks are available then the
corresponding mode is also set as DSC capable. This step is uncalled for
in a non-DSC panel scenario and might lead to unexpected behavior. This
change checks for panel DSC status before updating DSC book-keeping and
capability for the mode.

Change-Id: I30d6a4d7f3e772b7b13fcca6e318e96372a8becb
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
2022-07-27 12:27:03 -07:00
Sandeep Gangadharaiah
603ae09669 disp: msm: dp: update DP aux state with correct status
End section of the display post enable which is supposed
to do the cleanup before exit is also setting DP aux state
as powered on and notifying the connect as successful.
If there is a race condition between connect and disconnect
paths then the code execution would skip to the end section
since display is already disabled. In this case, the DP aux
state would be misleading. This change will set the status
and notify complete only during success case.

Change-Id: I1eca511e042d2dea619bf85fcc28adf9e0cc9536
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
2022-07-26 21:15:48 -07:00
qctecmdr
b7c83aa3f8 Merge "disp: msm: sde: fix cwb output res with DS & demura tap point" 2022-07-26 16:45:31 -07:00
Sandeep Gangadharaiah
6493a3623a disp: msm: dp: update debug message for mst conn id debug node
Incorrect debug message is printed when mst con id is set to
the desired conn value. This change skips printing debug
message during this scenario.

Change-Id: Ia7161ff2e7b8fba2da9757360d0c756cbe5ef166
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
2022-07-26 10:57:50 -04:00
Veera Sundaram Sankaran
5df608899c disp: msm: sde: fix cwb output res with DS & demura tap point
Add the missing concurrent writeback output resolution setting,
when destination scaler is enabled with demura tap point.
Additionally, move the dnsc_blur enabled check to the top as
that takes precedence.

Change-Id: Id0e851703ce6e1d8b7caffcdda69d7757222fc59
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
2022-07-25 11:39:04 -07:00
Amine Najahi
dd6baeb265 disp: msm: sde: fix UBWC stat error log format
Fix UBWC stat error log format to match number of arguments.

Change-Id: I08f1b7a13e370dc7cf3a5a9fc11c089f69e742b5
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
2022-07-25 08:05:57 -07:00
qctecmdr
ceaaff1fbd Merge "disp: msm: sde: avoid PM suspend/resume if display has splash enabled" 2022-07-24 05:56:34 -07:00
qctecmdr
2366eef20d Merge "disp: msm: sde: correct the sde vm release sequence" 2022-07-24 01:04:34 -07:00
qctecmdr
57cd9e59bc Merge "disp: msm: sde: avoid null pointer dereference" 2022-07-23 20:11:28 -07:00
qctecmdr
4f29acc9bc Merge "disp: msm: sde: set connector lm_mask for dp display" 2022-07-23 11:09:57 -07:00
qctecmdr
4e94573c28 Merge "disp: msm: sde: fix cwb lm allocation failures in RM" 2022-07-23 06:39:23 -07:00
Jayaprakash Madisetty
60053c51bc disp: msm: sde: avoid PM suspend/resume if display has splash enabled
With speculative retire fence, the first commit from HAL depends
on crtc power_on event instead of retire fence signal to unblock
the wait completion. Hence avoid triggering PM suspend/resume if
any of the displays have continuous splash enabled. This will avoid
any state changes in drm_atomic_state and will be inline with
HAL expectation.

Change-Id: I97360e3815651eefdd7e2c1494fa6e882df883b5
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
2022-07-22 15:01:13 -07:00