Add support to print illegal programming IRQ errors for 780 CSID.
Illegal programming Could be due to following reasons within a path.
1. User has to program either RAW formats or PAYLOAD on both
for multi VCDT with the second decode format. It can neither be a
mix of these.
2. Say in a multi VCDT situation for an active VC, the programmed value
of DECODE_FORMAT is PAYLOAD_ONLY (0xF), the value of DECODE_FORMAT1
should also be programmed as PAYLOAD_ONLY. Failing this check would
trigger the IRQ.
3. In a similar case, if both VCs and DTs are programmed to be same
values, the DECODE_FORMATs should also match.
4. User has to perform sensor switching with a new RUP. For
this, we need the MUP bit to be programmed along with RUP.
5. Early EOF enabled without VCROP registers programmed could also
trigger this IRQ.
CRs-Fixed: 2948116
Change-Id: Ib8cede8607d52586ef178c14a9a4bfd8d0b0b80e
Signed-off-by: Chandan Kumar Jha <cjha@codeaurora.org>
Decode format1 is required for payload decoding in
multi VCDT usecase.Format type is packed in 8 bits.
We will get 8 bits value as format type from UMD to
get decode format1.
CRs-Fixed: 2948116
Change-Id: I81bc816c1fc53ff8949d8920d076461ff1895e45
Signed-off-by: Chandan Kumar Jha <cjha@codeaurora.org>
For Mimas 2.0 TFE RDI port has a width of 128 bit compared
to 64 bit on Mimas 1.0. This change takes care of correct
packer format w.r.t rdi width.
CRs-Fixed: 2982472
Change-Id: I89b16dc517e68e5417ec4683a394b092ff0850f5
Signed-off-by: Vikram Sharma <vikramsa@codeaurora.org>
Earlier, constraint violation was received as part of image size
violation status. Add constraint violation check in vfe bus error
bottom half handler to accommodate changes to the bus irq status
register.
CRs-Fixed: 3005893
Change-Id: I62327b0900ecb3c05cb38a5079d6d9ffb8c5408e
Signed-off-by: Mukund Madhusudan Atre <matre@codeaurora.org>
In case of dynamic switch shdr use-case ensure discard config is only
applied on number of starting exposures. The change also avoids
programming fetch enable/disable via AHB if already programmed
via CDM at stream on.
CRs-Fixed: 2841729
Change-Id: I36719ca447eeb890f0059489709ab11dcc37dd38
Signed-off-by: Karthik Anantha Ram <kartanan@codeaurora.org>
Configure WM config to frame based mode for PLAIN16 formats in
case of SFE RDI WMs.
CRs-Fixed: 2841729
Change-Id: I8d21e593d13d46486fe3a1c03b51282efad015f0
Signed-off-by: Karthik Anantha Ram <kartanan@codeaurora.org>
Register read writes are expected to go through wrapper
functions in presil so that they can be overridden by presil
code. Change register read during tpg start to use this wrapper.
CRs-Fixed: 2932495
Change-Id: Ib72f2de381e096bde146e4fb1ff8f5187eaa5717
Signed-off-by: Mukund Madhusudan Atre <matre@codeaurora.org>
CAMIF SOF is subscribed as secondary event, change INPUT SOF
check to CAMIF SOF.
CRs-Fixed: 2986303
Change-Id: I0416c35c437edf75e86c3e6b0852ee1943415d2b
Signed-off-by: Karthik Anantha Ram <kartanan@codeaurora.org>
Based on arch, config flag can be set for presil and when enabled,
presil code will be compiled.
CRs-Fixed: 2932495
Change-Id: Iabf1a74be3582d0b84b70777e406b4ce02218220
Signed-off-by: Mukund Madhusudan Atre <matre@codeaurora.org>
Signed-off-by: Suraj Dongre <sdongre@codeaurora.org>
This commit fixes minor issues in logging in VFE and CSID drivers along
with major fixes and improvements -- issue CSID global reset after
fatal error, extending debug register parsing for IFE Lite, fix clipping
of text due to limited buffer size in RX error log printing.
CRs-Fixed: 2977145
Change-Id: I4eacfc60264911b0597ece7693877fc1fb6976eb
Signed-off-by: Anand Ravi <ananravi@codeaurora.org>
In burst read flow, we need to wait CCI irq
once one set data is read, but the fifo may has
new data what can be read immediately and don't
need to wait the irq. This change also optimize
the irq processing, we can reset irq mask first,
then process the irq status, it can avoids some
timing issue, e.g. the read context runs too
quickly, then read context enable the read
threshold bit in irq mask1, but irq context runs
late, then irq context clear the read threshold,
then we can't receive read threshold again.
CRs-Fixed: 2995920
Change-Id: I8acfadf07b95782725bf4bf8b05b88789874c1da
Signed-off-by: Depeng Shao <depengs@codeaurora.org>
Append sync obj's name to logs to help debugging.
CRs-Fixed: 2998236
Change-Id: I461865b72e49b11267c2dc20176985b4545a42e8
Signed-off-by: Sokchetra Eung <eung@codeaurora.org>
Update SFE output ports in buf done failure dumps.
Currently reg dump on error is triggered only on HW
error. Extending this to scenarios where the pipeline
is stalled possibly due to congestion.
CRs-Fixed: 2841729
Change-Id: I423bbac19efd5dd57d998b7017d9bfcff23392d0
Signed-off-by: Karthik Anantha Ram <kartanan@codeaurora.org>
Append workq name in workq delay detect API to identify
which workq is scheduled late. Create workq name macros for
cci and cpas to pass to workq delay detect API.
CRs-Fixed: 2994927
Change-Id: Iebc14520b918272e92b59c900de5fe17f38a2406
Signed-off-by: Sokchetra Eung <eung@codeaurora.org>
AHB WD modules only support async reset. In order to clear
WD without complete camera reset disable and clear
WD interrupt. Kernel driver subscribes only for WD0, this
change adds this sequence only for WD0.
CRs-Fixed: 2841729
Change-Id: I0913d20fc3bd4bf911484efa42fb5889e539fea0
Signed-off-by: Karthik Anantha Ram <kartanan@codeaurora.org>
Notify all the connected devices, when the link is stalled.
CRs-Fixed: 2841729
Change-Id: I08cbb587071f4bfd6e1cdefddffb66a83ba8c187
Signed-off-by: Karthik Anantha Ram <kartanan@codeaurora.org>
