Send ife process frame event from IFE HW manager for presil
which pchost depends on to start IFE frame runcore or regdump.
CRs-Fixed: 3212166
Change-Id: I268059ec490b2a95f0626045eed26192eb0a42a2
Signed-off-by: Joshua Florez <quic_jflorez@quicinc.com>
Signed-off-by: Suraj Dongre <quic_sdongre@quicinc.com>
This change uses half frame interval as workqueue congestion
detection threshold and record the last trigger time before
sending req, we can get correct last tirgger time in this way.
CRs-Fixed: 3237172
Change-Id: I2d583f7758062340fe6b0c598bfa7e90f49211c2
Signed-off-by: Depeng Shao <quic_depengs@quicinc.com>
LCR enabled flag is not reset during flush and the corresponding
register is also not reset. It could cause random behavior after
flush.
This commit resets LCR flags during flush.
CRs-Fixed: 3241884
Change-Id: I8821656ae7baf97a59cdc57bb79ded9552185f08
Signed-off-by: Gaurav Jindal <quic_gjindal@quicinc.com>
camera-kernel:
361b933 Merge "msm: camera: isp: Get correct csid core info" into camera-kernel.lnx.dev
7b70890 Merge "msm: camera: sensor: Unregister i3c driver properly" into camera-kernel.lnx.dev
e6cfde7 Merge "msm: camera: isp: Use correct resource count to release resource" into camera-kernel.lnx.dev
3c07ce5 Merge "msm: camera: sensor: Power down sensor if unlocking or locking sensor fails" into camera-kernel.lnx.dev
f88c28b Merge "msm: camera: jpeg: Increase the max context number to 24" into camera-kernel.lnx.dev.
Change-Id: Id0cbb28870ca07c49822c3c13c496f4ec090f176
Signed-off-by: Haritha Chintalapati <quic_hchintal@quicinc.com>
The core info in hw info structure pointer to
csid hw, we need to get correct core info from
the private data of match dev.
CRs-Fixed: 3234793
Change-Id: I4f295c6eb206a0a61fb923b1e04bd00786dbfccf
Signed-off-by: Depeng Shao <quic_depengs@quicinc.com>
Sensor remains power-up status even if unlocking or locking sensor fails
while probe, now we will power down sensor in case of that.
CRs-Fixed: 3228473
Change-Id: Iab6edf0a824c61132211c3ea5c46cc0fff0247c4
Signed-off-by: Stark Lin <quic_starlin@quicinc.com>
Customer may have more than 3 physical cameras, and userland
may also create multi jpeg pipelines, so increase the max
context number to 24.
CRs-Fixed: 3228532
Change-Id: Ia90947f03a1543f19684aa7cad1b1972419e9c74
Signed-off-by: chengxue <quic_chengxue@quicinc.com>
Only unregister the i3c driver if there is i3c node
in dtsi.
CRs-Fixed: 3234792
Change-Id: I01e99406a08648aab90147d1287d3d8b6ab04e89
Signed-off-by: Depeng Shao <quic_depengs@quicinc.com>
SFE resource count isn't fixed, it is less than the max
supported resource, we need to use actual resource count
to release the resource.
CRs-Fixed: 3234791
Change-Id: I7cb16f3d8120451cac1bfc226f6849268f3b5c46
Signed-off-by: Depeng Shao <quic_depengs@quicinc.com>
If we set burst write method to write sensor word data type
register data, some 32 bits data queue cannot be filled full,
and invalid data will be injected into data queue, then cci
burst write will fail.
CRs-Fixed: 3221426
Change-Id: I20ff1e7f508e4bbc79826db7faa13fcc80eaaf96
Signed-off-by: chengxue <quic_chengxue@quicinc.com>
5d46ed4 Merge "msm: camera: common: Add logs in wait for completion wrapper" into camera-kernel.lnx.dev
10e9403 Merge "msm: camera: icp: Compute and log FW avg response time per ctx" into camera-kernel.lnx.dev
947caff Merge "msm: camera: memmgr: suppress set mapped dmabuf name failed log" into camera-kernel.lnx.dev.
Change-Id: I08a21963557700bf859ffffc0629d510f751b560
Signed-off-by: Savita Patted <quic_spatted@quicinc.com>
Compute and log average firmware response time per context to
measure firmware latency.
CRs-Fixed: 3223208
Change-Id: Iaf27a43259fc2a558fdd59165f8afdd4f8e5f6e7
Signed-off-by: Sokchetra Eung <quic_eung@quicinc.com>
Create a Macro to wrap around wait_for_completion_timeout to
log start and done wait time, and caller's customary error log
if timeout happens.
Modify all wait_for_completion_timeout in ICP hw mgr to use
this wrapper.
CRs-Fixed: 3227018
Change-Id: Ief2c52e69954c653d9cbced8acd823b436bab086
Signed-off-by: Sokchetra Eung <quic_eung@quicinc.com>
we can't set dma buffer name when it has been attached to hardware.
As usually UMD allocate one buffer then map it at KMD side. So most of time,
set mapped dma buffer name failed. But it's not a fault error. So
we move log to debug level.
CRs-Fixed: 3219506
Change-Id: If635f9fbeb26b96f45c83b1d03cbba97576c92b2
Signed-off-by: Fengjie Chen <quic_fengjiec@quicinc.com>
The change handles tasklet scheduling delays in buf done handling.
If there is a scenario where in we have a request N in active list,
and N+1 is applied on the output frame for N. It's possible
that after applying N+1, the buf done tasklet for N is not scheduled
in time, and if it so happens that the tasklet is scheduled
out beyond the next frame, HW would have consumed N+1, and we
end up reading the last consumed addr for N+1 in the buf done bh for N.
The read last consumed address from N+1, will never match with N
ultimately stalling N. We could read the last consumed
addr registers in top half, but that would lead to increased
register reads in ISR, delaying top half processing therefore the change
handle such delays within the ISP state machine.
The underlying understanding here is if HW has generated buf
done for client X on request N+1, it's bound to have processed the
buffer for client X on request N.
CRs-Fixed: 3223063
Change-Id: I1e96f5b51b6fc388f3c189f882f8ae543a6ccb06
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
To achieve sync state, platform probe needs to happen for i3c-i2c
nodes since platform devices are created for them due to topology.
Return success in component bind for i3c-i2c based sensor nodes.
CRs-Fixed: 3227008
Change-Id: I6604fac1ef605f7d3cef69954238ac62bee77dae
Signed-off-by: Mukund Madhusudan Atre <quic_matre@quicinc.com>
Do not call register with owner when device id table is empty.
CRs-Fixed: 3227008
Change-Id: Ibb86154c4c4f0b0e3d81867eb1ed049eefbc1a85
Signed-off-by: ridhshah <quic_ridhshah@quicinc.com>
Fix the argument order for SFE bus deinit calls.
CRs-Fixed: 3218412
Change-Id: I7ecda25aae455e0d9302b7f379ec019053a34e92
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
The drv and bw voting blobs are handled by isp generic blob
handler, so need to skip for sfe blob handler.
CRs-Fixed: 3065551
Change-Id: I467d16818d2807194e3c7b62bd6b2b1eb06b4759
Signed-off-by: Mukund Madhusudan Atre <quic_matre@quicinc.com>
Currently during csiphy component bind, we are allocating memory for
csiphy register info structure, which is not required, since the
structure in statically defined in headers. This causes panic during
unbind calls, since we are supplying address to statically allocated
memory that we previously pointed to, during bind. Remove dynamic
memory alloc and free to fix this issue.
CRs-Fixed: 3223335
Change-Id: If5d029dae4660b4a57b007c895956baceac9e4b5
Signed-off-by: Mukund Madhusudan Atre <quic_matre@quicinc.com>
Get the shift mask from the corresponding chipset header.
CRs-Fixed: 3226910
Change-Id: I45f439e7b7ec23096ecb31f2b94cf76189669e7f
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
Move CSI_3PHASE_CTRL registers from common to data rate
specific config.
CRs-Fixed: 3226880
Change-Id: Id39c2f4fe436cdbed99cfc407c79ae3cd7fccdbe
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
Fixes LDAR dump for ISP active requests by passing in the correct
address to dump helper function.
CRs-Fixed: 3215380
Change-Id: I1b4ad1c041cc3c965e7f95f9ef8129e26dce5344
Signed-off-by: Joshua Florez <quic_jflorez@quicinc.com>
camera-kernel:
3f04ee0 Merge "msm: camera: isp: Reorder the stream on sequence in LCR use case" into camera-kernel.lnx.dev
f7b2922 Merge "msm: camera: common: Use CAMERA DLK override for compilation" into camera-kernel.lnx.dev
5dbda18 Merge "msm: camera: req_mgr: Handle bubble case in tasklet context" into camera-kernel.lnx.dev.
Change-Id: If94d294a291108fb14e0d2e49824a8e85df8e51c
Signed-off-by: Savita Patted <quic_spatted@quicinc.com>
To be able to disable camera compilation on newer targets,
use DLKM_CAMERA_OVERRIDE in camera makefiles to control
compilation.
CRs-Fixed: 3219745
Change-Id: Iaf9518457a690554aca21fc1c6ebb3324d0dac46
Signed-off-by: Pavan Kumar Chilamkurthi <quic_pchilamk@quicinc.com>
Due to timing protocol constraints between LCR and PD resources and
sof retiminig disabled, PPP resource should be enabled after RDI0
whenever LCR is enabled.
This commit changes the order during the CSID start to enable PPP
after RDI0.
CRs-Fixed: 3222469
Change-Id: I11371ea4602ff4bd72e690453103bd6a18ba836a
Signed-off-by: Gaurav Jindal <quic_gjindal@quicinc.com>
Mark bubble flagged slot as applied state in tasklet
context.
Due to scheduling delay, CRM bubble process error
work-queue is taking more than 60ms for scheduling.
We had received back-to-back epochs due to tasklet
scheduling delay which invoked process requests for
applying further requests.
We reset the Nth-3rd slot during the process request.
We had done slot reset for bubble requests during
process request call as process error work-queue yet
to schedule which had to mark the slot as the
applied state.
CRs-Fixed: 3191903
Change-Id: If8154b7de8b3981fc9de64be2cd400c7b432c571
Signed-off-by: Chandan Kumar Jha <quic_cjha@quicinc.com>
This change involves the parsing of domain-id mapping
from DT and storage of this information in struct
cam_cpas_private_soc. This information will be relayed
to userspace in an ioctl call, and also exposed to the
IFE driver within the kernel.
CRs-Fixed: 3215167
Change-Id: I68d914fd4b84bc029edccd5cd1d2e2733fa32fcd
Signed-off-by: Li Sha Lim <quic_lishlim@quicinc.com>
Other than stat WMs, all other clients can run in secure mode.
CRs-Fixed: 3208187
Change-Id: I17956a4815a56eacbaa14e08db98fde681a6d9d6
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
Add memmgr interface and support to allocate buffers from
ubwcp heap.
CRs-Fixed: 3197463
Change-Id: Ic3368e5ff81710dba795c9625f9a461833f915e3
Signed-off-by: Pavan Kumar Chilamkurthi <quic_pchilamk@quicinc.com>
Add ioctl interfaces to support dma begin and end cpu access
operations for camera buffers.
CRs-Fixed: 3197463
Change-Id: Ibeb31e8f425489abfdd47df6f92271ac40ace407
Signed-off-by: Pavan Kumar Chilamkurthi <quic_pchilamk@quicinc.com>
Add support for 32 bits wide sensor ID for CCI hw during sensor
match ID operation.
CRs-Fixed: 3210196
Change-Id: Idef7f5cd3d7199198d0c6aa06ce54415a409d147
Signed-off-by: Jigar Agrawal <quic_jigar@quicinc.com>
Some unhandled buf dones belong to next req, we need
to add them to deferred buf done list and process it
in future.
CRs-Fixed: 3197114
Change-Id: I5489cb6faacf2b6c9018b3b660a1df2ee6ac9564
Signed-off-by: Depeng Shao <quic_depengs@quicinc.com>
* changes:
Snap for drop 06/09/2022 mainline 783 LA.VENDOR.13.2.0.AU237
msm: camera: common: Enable config for rpmh calls
msm: camera: common: Add debug infrastructure for camera drv
msm: camera: common: Add support for DRV config
msm: camera: common: Add support for bw update blob v3
msm: camera: isp: Read back and update top debug cfg register
msm: camera: icp: Log all active requests on enomem from FW
msm: camera: csiphy: Add support for RF channel based csiphy settings
msm: camera: common: Add I3C Driver support
msm: camera: isp: Remove IFE HW mgr reference from ISP ctx
Update sync headers to remove third party update for year 2021.
CRs-Fixed: 3207212
Change-Id: I30d029d5755d4fb129c256f9771b20c115970388
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
