Added unique irq name per pci slot so that affinity settings
can be altered as needed. Pci id will be read from dts, and
when there is no entry in dts, default value 0 will be used.
Also for all other target types except qcn9000, default value
0 will be used.
If WLAN_MAX_PDEVS is defined to 1, then always return pci id as
0 since there is only one pdev present
Change-Id: I8159ec8d8daecae687fcc286d620bfe9861dff98
Add support for HW version soc id and HW name string
for Hastings and HastingsPrime platform.
Change-Id: I1ba57339b2f9afd425e1ecc9f312ad484340d226
CRs-Fixed: 2681134
Currently as part of runtime PM, only the active
tasklets are being drained. For chips eg. QCA6390,
QCA6490 etc, there are grp_tasklets and delayed reg
write work which has to be drained before entering
runtime PM.
Add the logic to drain all the possible tasks
before entering runtime PM.
Change-Id: Ieb486f00fffd7346dcdc1faea6fed5850ef6daf7
CRs-Fixed: 2676000
Reduce the number of CEs used in IPQ5018 to 6 since it has only
one mac and requires only 6 CEs. CE7 and CE8 are reserved for FW
and not needed to be configured from host.
Change-Id: Ibe262c32d8b3234873391559d939bc198c658c60
Commit c81a71e488 ("qcacmn: Cleanup and refine runtime PM open/close
logic") addes the change to align default usage count for both runtime
PM enabled and disabled cases. So active usage count for runtime PM
enable case is 0 and for disabled case is 2. Refine the usage count
checking logic based on that change.
Change-Id: I4e78089760a28d10e6b37bb1a7b2d5242de6c111
CRs-fixed: 2676761
Do not vote for PCIe link for QCN7605 to allow PCIe
bus to go to low power mode.
Change-Id: I14e1a5d142497e3cbe8ed12874a428ab7d90afed
CRs-Fixed: 2649897
Change the error level logging which are called by holding
the spin_lock to debug level to avoid printing to console.
Change-Id: If057087e808ed49000eba8b9795397a0cf35a357
CRs-Fixed: 2676235
As part of HIF runtime PM close add assert to make sure no runtime
PM user has missed any put which may lead to runtime PM getting
disabled at runtime. This assert ensures all runtime PM users
have get and put in sync.
Change-Id: I6663be013e85b8a262ccc0f60c8bd9c59bac25ef
CRs-Fixed: 2665231
Runtime PM code has been refactoring multiple times so some open/close
logic may be duplicated and messed up. Cleanup and refine the logic.
In other to align both runtime PM enable and disable cases, make sure
default usage count is always 2 and sanitize the same when runtime PM
exit. hif_pm_runtime_stop() should always happen from HDD disable power
management APIs so clean it up from hif_pm_runtime_close().
Change-Id: I3b64369608c2d9aa4b3353503c12e0d05a57b592
CRs-fixed: 2666196
Add prefetch_timer configuration for CE rings.
Set prefetch_timer=1 configuration for qca6490 destination CEs,
prefetch_timer=0 configuration for other targets CEs.
Basically setting to 1us asking CE hw to update ring tail pointer to
update within 1us. FW side CE SW sets all rings to 1us already.
Idea behind this change is, we have seen pre-silicon issue where SRC
ring TP read by SW was not seen updated value when prefetch was set
to 8us. Changing prefetch timer value to 1us helps to resolve
pre-silicon issue.
So host side rings need to update the prefetch timer to 1us.
Change-Id: I0830c73517c29cf39e6b2974bf3faa44e5673741
CRs-Fixed: 2669762
During initialization of driver, the runtime pm usage
count is incremented to 1 when the pm state is NONE.
Runtime get is done as part of htc send packet for
a wmi command in scheduler thread context. In kworker,
runtime_start is processed as part of driver load and
runtime put is done prior to updating the pm state to
ON. Runtime put triggered as part of htc send packet
causes a panic since the state is NONE and usage
count is 1.
Fix is to set runtime pm state to ON prior to doing
a runtime put as part of initialization.
Change-Id: I52cca5240f2f0872c681aab3a58a382f3fa1df0e
CRs-Fixed: 2669029
In order to avoid panic in hif_pci_runtime_pm_warn(), call
qdf_is_fw_down() to check if fw is down. If fw is down, return without
panicking.
Change-Id: I3fd3e0334220c1cf3ae6b3ec3fd5b1ede1705013
CRs-Fixed: 2664133
Change DP interrupt names to unique values so that
interrupt affinity can be adjusted based on this. This is
similar to what is being done for Copy Engine interrupts.
Change-Id: I7f1789c8c0103e7c01b0a2956a7a37149c7462d1
Currently, athdiag can't work with QCN7605.
Thus made below change to make it work:
1. Skip pci address boundary check for QCN7605 as QCA6390.
2. Make QCN7605 access target memory via QMI.
Change-Id: Ibfcccb57486c99d78c02e322c4e2ae1a7c8dab81
CRs-Fixed: 2653814
Currently there are cases where the CE status ring
head pointer is incremented, but the corresponding
buffer in the CE DST ring has nbytes as zero. This
can be a possible case where the head pointer was
updated before the DMA copy was completed and before
the nbytes could be updated with the number of bytes
copied to the CE DST ring buffer.In such cases we
haven't processed this entry, and hence should not
increment the tail pointer.
Hence we do not increment the tail pointer if
there was no data in the CE DST ring. Also
enable the logging of CE STATUS RING REAP
even if the CE DST reap was not successful.
This will help identify the cases where the reap
was not successful because of nbytes being zero.
In Success case, the CE desc history will show
STATUS_RING_REAP and DST_RING_REAP events.
In nbytes=0 failure case, the CE desc history will
show STATUS_RING_REAP event with HP moving ahead,
but the TP will not have moved.
Change-Id: Ibc3145142b6c88f6da3e12748d0ac8090486e8e3
CRs-Fixed: 2657285
Update QCA_NAPI_DEF_SCALE_BIN_SHIFT for defconfig builds to
the same value as the perf build.
Move the WLAN ext irqs to gold cores for defconfig builds.
Disable cpu isolation before moving the IRQs to gold cores.
Add the ability to move IRQs to gold cores when the cpus
hotplug in.
Change-Id: I4cfecd02a1a2200dc99adee9a324b90c877c13fd
CRs-Fixed: 2638820
This is to enhance statics for runtime put/get, which is
to detect if there is mismatch for usage_count.
Change-Id: I24cddb9d10e4cb675c8375cbd0f589c7718bd680
CRs-Fixed: 2647972
Macro DMA_COHERENT_MASK_IPA_VER_3_AND_ABOVE is used in non
IPA offload case also so bring this macro definition out of
IPA offload feature and change it to DMA_COHERENT_MASK_DEFAULT.
Change-Id: Ib03aa8ae2938e1de1a957660923a711d452a9337
CRs-Fixed: 2649909
Add HIF_INFO to log the linkstate_vote value in the hif_vote_link_up()
and hif_vote_link_down() functions in order to log the occurences of
the rare event when we vote for link up/down.
Change-Id: I7549b3400977583bd2cd4ec4fcb3f16dd0865ce7
CRs-Fixed: 2648860
Currently HIF runtime PM APIs will check runtime PM enablement using
pm_runtime_enabled() by checking for disable_depth which can be changed
at any time. This may cause usage count imbalance since the HIF API may
skip calling the corresponding runtime PM framework API to increase or
decrease usage count. Enhance runtime PM enablement check so that it
will always honor WLAN ini config first.
Change-Id: I4b2863ef7fa0dcd6fd61b776e6cb0ab109ffb3ec
CRs-fixed: 2647986
Disable the PCIE scratch reg read/write to wake up PCI bus.
This fixes the PCNOC error seen during boot up on writing to
the PCIE scratch register.
Enable DEVICE_FORCE_WAKE_ENABLE feature flag to enable
PCIE sracth reg read/write.
Change-Id: If4efd0afbddf97462bf9d0f06d0085c0a5b37a64
CRs-Fixed: 2636160
Initial changes for ipq5018 compilation.
Added device ID and target type checks for ipq5018 traget.
Change-Id: Ib86a371fbe66749fcb6d114e7a4a9931b684e03d
Add below change:
1 log level change from error to debug level in
hif_pci_runtime_pm_warn.
2 Change warn_on to bug_on in hif_pci_runtime_pm_warn.
3 change pm_stats to atomic
4 record last 128 caller both for get/put
Change-Id: I2dae883dfaed22812445c5d50920fb363b9e0ea7
CRs-Fixed: 2638863
Use pfrm_disable_irq_nosync/pfrm_enable_irq APIs inplace
of disable_irq_nosync/enable_irq to enable/disable IRQ.
Change-Id: I4002a0c8efddac7211ab0c7e8b92356b0c7bc7bf
CRs-Fixed: 2636512
From Genoa firmware request, in order to improve
the IPA througput, increasing the number of copy
engine 8 entries and other nbytes values.
Change-Id: Ib1ae170c3b3f5af61d03ad8a60bc616b7a58a725
Add HIF APIs to prevent or allow link to go into low power states. The
current implementation uses PLD APIs to make the needed configuration.
Change-Id: I22efb4bcf902f9aff674ed1872f4f23bef508aae
CRs-Fixed: 2602029
For qca6750, update the SHADOW REGISTER OFFSET value and
fix the compilation issue.
Change-Id: Ic4b44c1c40e62ddcc50c0a66d37c0663a70b5c54
CRs-Fixed: 2633044
Currently, Genoa CE4 is using interrupt mode. Host will not require
IRQ base on current CE configuration and change below:
"Change-Id: Icabe68298737dc412949484f6d3fdcd8c05910d5", which cause
no IRQ handle of tx completion and source ring full, blocking
TX finally. To unblock TX, correct configuration of CE4.
At the meanwhile, this issue expose another problem that the polling
mode seems doesn't work. Will scope it on another thread.
Change-Id: I31eed8806b939a12503bb4ddd8b9dec85f3c3540
CRs-Fixed: 2602888
Since it support PCIe shadow register for QCN7605,
and these shadow register also falls below 512K,
which can be used for IPA write directly without
windowing. So don't use the temporary PCIE_PCIE_SCRATCH_2
for IPA GSI write now, insteadly, passing the correct shadow
register of copy engine 5 to IPA.
Change-Id: Ica3a502b96e98ee6c07c1032760b5dcb512957d8
Add HIF changes for supporting the newly added USB bus type
for Genova.
FW team need athdiag tool to operate FW information. Host
driver need to pass the command and result between athdiag
tool and FW.
Change-Id: I6158a9f8c723a797d39beca09a913c7cb9e10025
CRs-Fixed: 2595515
Allocate a buffer of size 4096 bytes for each buffer
posted to CE2 source/destination ring.
Change-Id: I0beb1e4e87c19508917e8564b441819031be2065
CRs-Fixed: 2619899
QCN7605 has 2 set of shadow registers, WCSS block and PCIe block.
As PCIe shadow register are at power domain boundary, enabling
PCIe shadow register for QCN7605.
Also PCIe shadow register falls below 512KB, no need to use register
windowing which is required to get it access from IPA FW
Change-Id: If18d2d0a3f16f492b3c32449695e70c2b9942375
CRs-Fixed: 2623853
Currently, the IPA GSI can't update the index to copy
engine 5 write index register since such kind of
register address is above 512k, so as a workaround,
we use PCIE_PCIE_SCRATCH_2 to replace copy engine 5
write index register for IPA update the index. And then
WLAN firmware will poll this register to check if this
index update or not, if updtae, WLAN firmware will be
as agent to update the index to real copy engine 5 write
index register, and then the data from IPA to WLAN will
work. Before the real fix is ready, we use this method
for workaround.
Change-Id: I383a7d52f5685b633f1bd44659b11f30231c8ca8
Update CE registers offset during hal srng configuration
and configure CE IRQ for qcac6750.
Change-Id: I4fd3d37783361f0029c7ef80e32425f8790d1250
CRs-Fixed: 2617699
Genoa FW use the hardcode 128 for ce5 destination ring
entries, so change host code to follow up with it.
Change-Id: I1b7e70f8244efc3d3ca3dc659fb3d7687828b9c4
Fixing compilation issue for USB interface on non-
msm platform by adding pld_common.h header file in
if_usb.c which contains cnss pld specific definitions.
Change-Id: I67b3fd29bb21d827618655f337f38beb683a4c41
CRs-Fixed: 2615907
Added new qca5018 hal folder to add ipq5018 specific changes.
This includes interface files to access ipq5018 hal registers.
Change-Id: I7e19dc7c8719fa175695b268dc904fb4521a3330
This is a public API, so move it outside to hif.h file so it can be
used elsewhere as well.
Change-Id: Ic870cf804df69f6d7bb5a792da662759d687e0ed
CRs-Fixed: 2616491
Replace QCA_WIFI_QCA8074_VP with CONFIG_WIFI_EMULATION_WIFI_3_0
since VP platform is not being used anymore.
Most of the parameters present inside QCA_WIFI_QCA8074_VP are related
to emulation timeouts. Hence replacing it with a more meaningful flag.
Change-Id: I22a0e5803e765333947f1613b376dcc6bd25b5af
