Coherency check is done for all kernel revisions during
begin_cpu_access, but the check is limited to older kernel
revisions during end_cpu_access. Fix it to have the
coherency check for all begin & end cpu access.
Change-Id: I03ada0d7dea6875f0be7b4f807738480bcfb3c70
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
Enable DP AUX IPC logs for GKI builds to allow more complete
log collection.
Change-Id: I2f61c167d5856f1d310b4c7145cb18dbb5d7d6dd
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
This change adds detect_ctrl to tear_check block and
programs it to its default configuration.
Change-Id: I7665b373a6cd846bf5979c2dc02bc0bdfdf309ab
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
This change avoids wait for EPT to timeout in non-qsync panels
when the EPT time is within last & next expected vsync time
calculated based on current fps for panel.
Change-Id: I9e385c14a20994b29b5bc4afb024f147e6cc035c
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
During drm_bridge_mode_fixup, we deny a simultaneous crtc state
change and seamless variable refresh. Incorrect translation logic
between drm_mode and dsi_mode made it such that whenever the dsi
bit clock is not the default value, any drm commit would be marked
with the variable refresh flag, denying all suspends. This change
fixes the suspending issue.
Change-Id: If3c1f603af3e2917f82be6487bee1084a6e1b605
Signed-off-by: Kirill Shpin <quic_kshpin@quicinc.com>
Extension bits of test point selection is needed when test
point value exceeds three bits, not based on blcok id value.
This change fixes debug bus test point selection when
value is more than 3 bits and extension bits are required.
Change-Id: I37688b2c6e476b1271daad0bbddb5896edc530d1
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
Set the number of layer mixer for each wb mode based on the
current mode hdisplay width. If the hdisplay width of current
mode is greater than the maximum layer mixer width of HW supported,
set dual layer mixers for this mode and check if the split
hdisplay width is an even number.
Change-Id: I0190830ed559f008f9e2c0752858ddc5e7cb83cd
Signed-off-by: Lei Chen <quic_chenlei@quicinc.com>
In userspace, the backlight scale of LTM will be set to the maximum value
in the suspend case. However, sometimes this value is sent to the driver
after resume. This will cause a backlight flicker issue.
For fix this issue, this change resets the backlight scale in the suspend case.
Change-Id: I0eb586eeefbf3444d6f44281d58789460300dffc
Signed-off-by: Yuchao Ma <quic_yuchaom@quicinc.com>
The driver currently inserts a failsafe mode when EDID read fails
for SST. But for cases where the edid read succeeds but all the
modes are getting filtered out because of resource availability,
the driver does not add the failsafe mode. But the usermode
expects the failsafe mode to be always present in the mode list
as per DP specification. Also, the driver currently does not
add the failsafe mode, if the edid read fails on an MST monitor.
This change covers all these missing cases and makes sure the
failsafe mode is always in the connector's mode list if it is
in connected state.
Change-Id: I92eeaa00ad7b26a18b3689aa1c2ada4244aba3bc
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Allocate DSC inversely for non built-in displays to avoid Quad DSC
can't be contiguous reserved as the below scenario.
Use case: Primary display with 2 DSC, and DP display can support 8K@60
with 4 DSC and 4k@60 with 2 DSC.
--> when both display are in powered off, all DSC blocks are free.
--> enable DP display with 4k@60.
DSC 0/1 is allocated by DP display
--> enable primary display.
DSC 2/3 is allocated by primary display.
--> switch DP display to 8K@60
DSC 0/1 + DSC 4/5 are allocated by DP display.
But the DSC must be contiguous allocated for Quad pipe.
Change-Id: I465c115bb7ec775483dc6a984306a9aa51750b14
Signed-off-by: Lei Chen <quic_chenlei@quicinc.com>
Demura backlight value will be updated based on the backlight event
in the driver. Make HFC gains programmable based on backlight value.
Signed-off-by: Mitika Dodiya <quic_mdodiya@quicinc.com>
Change-Id: I74e9aa2c274eedb473095c5eafef194d6a6f1d94
Currently, ctrl lock is taken while waiting for CMD DMA done even in
case of ASYNC command transfer, which doesn't allow any other operation
on the controller until the command transfer is done. Avoid this by not
taking ctrl lock while waiting for CMD DMA done.
Change-Id: I91f2638fa02f48ec4c7a41c750daa46b52c5e2f2
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
When calculating the number of DSC slices based on the source
and sink capabilities, the driver is using an incorrect check
for max slice width which results in increasing the num of
slices if the width is an exact multiple of 2560.
Change-Id: Ia854c4a2d436144165fb52beb04b5e0d1678d0f6
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
To optimize evt log entries, spinlock is been removed and
used atomic operator for curr variable, due to which there
is mismatch of count values between curr and last variable during
xlog dump in kernel. So change the last variable to atomic to
avoid race condition between entries of evt logs.
Change-Id: Idf3e2b982261d77fec97985af1e8bf740a6f6197
Signed-off-by: Ryan McCann <quic_rmccann@quicinc.com>
Update the string formatting of debugbus dump header
to support existing scripts for debugbus parsing.
Change-Id: Ie0b4fdcb73e131ea5893a3dbc6aad969735d137d
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
During HPD High, the driver sets the CONNECTED state and then performs
a sequence of initialization operations. If any of them fails, it should
properly unwind the executed operations to restore the driver to its
initial state. This change adds error handling paths in the hpd high
handler to do just that.
Change-Id: I66a77ff73b7c11d0a59d80b8df3c4ea49a4ed3a6
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
During qsync frequency step down, it is possible for the changing
frame window to lead to frame buffers being transferred when it
is unsafe to update. Pineapple r2 hardware supports using the
panel's TE level, instead of the start window, to trigger the
frame transfer.
This change enables using TE level during QSYNC or AVR, if the
hardware supports it.
Change-Id: Ie675edaaeb80921c639905395b709f4c67134fc7
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Reduce the MDSS IRQ processing latency by skipping the status
register read/write of the interrupts which are not enabled.
Change-Id: Id86057ad3ab043ad76d4d4b44a373eff3b55da4d
Signed-off-by: Shirisha Kollapuram <quic_kshirish@quicinc.com>
Add dsiclk_sel support for both DPHY and CPHY, update pclk_div
calculation w.r.t dsiclk_sel as per HPG.
Change-Id: I573addd62c77d1c9f089b7aadf386cd2e579f442
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
Signed-off-by: Kirill Shpin <quic_kshpin@quicinc.com>
