Testing of the SPR feature shows IPC restore frames where partial update
programming is not applied. This is a result of the pre-IPC cached ROI
region being used for filtering of CRTC ROI changes.
Update the CRTC cached ROI logic to clear the cached ROI on IPC events.
This ensures color processing partial update logic handles the post IPC
frame with a clean state.
Change-Id: I4e337bd150d02e4c8934ca04c0d632d5ad71dd5d
Signed-off-by: Christopher Braga <quic_cbraga@quicinc.com>
When there is CPU processing delay between first INTR clear and
second INTR clear there is a chance that the second register
write might clear the next frames interrupts which will avoid
triggering the irq callbacks causing software hung. This
patch avoids such a scenario by removing such double clearing
of INTR registers.
Change-Id: I8407991769c69d2d2c691763240671d5f3c0416d
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
DPU driver registers core clock with MMRM driver for clock
mitigation policy. In the event that MMRM driver is not enabled
then mark dpu driver clock as non MMRM type.
Change-Id: Id4dd4a512c81ba54514171867852531f00604a66
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
In case of underflow/overflow IRQ storm, send panel dead event from
scheduled underflow and overflow workqueue handler.
Change-Id: Ic6cd6cbae097ea970a392fa99e30b3b620633d40
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
After triggering dynamic refresh, if there is any dsi_ctrl_isr, dynamic
refresh done status also gets cleared as part of it. Because of this,
wait4dynamic_refresh_done timeout error is seen even though dynamic
refresh is done successfully.
Change-Id: I39b42c60d15d9cb0557669f95ff2ed83989f9cd3
Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
While transition from very low fps (1Hz) to higher fps (120Hz)
there will be a delay on first frame to take effect on
mode switch. In such cases if kickoff_timeout value is programmed
based on newer high fps wr_ptr_timeout can happen. To avoid this
update the kickoff timeout with respect to lower fps and reset
it back according to present fps once the mode switch commit is
done.
Change-Id: I08e1a68bb1e388a1bda8ef61d47e9eb4b2fc97fe
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
Check that link clock is enabled before attempting to enable
stream clocks.
Avoids NOC errors when a disconnect is triggered while a modeset
operation is occurring.
Change-Id: I12d363261d4f36bf7d3149b77a917ecfa0e7b8ed
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
If cont splash is enabled, wait for autorefresh_status to be idle for
1 vsync in prepare kickoff. This patch also prevents entering to
rsc_solver_mode if autorefresh_status is busy.
Change-Id: Id7491361dae2482905e10a5a10e590d5f5b49e6f
Signed-off-by: Yojana Juadi <quic_yjuadi@quicinc.com>
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
This change stores the connector id before the connector
is set to NULL in post_disable.
Allows tracing through of a single connector's disable
flow in a MST scenario.
Change-Id: Ibf4079ea75c9e0643d0d9976289ab6983509ee93
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
Partial update of SPR CFG 5 is showing intermittent odd
behavior. Move CFG 5 programming to AHB path to resolve
the issue.
Change-Id: I0719de9ea29ffe2f75c072053162133681a1b007
Signed-off-by: Christopher Braga <quic_cbraga@quicinc.com>
When wfd display is connected, qseed3 coefficient lut programming
is getting erased due to idle pc entry for wfd pipes. On idlepc
exit commit, plane properties are not reconfigured from userspace
since support is not present for writeback crtc. This patch
updates idle pc handling to avoid gdsc power off when writeback
crtc is connected and for CWB encoder gdsc power off will happen
on idle pc entry.
Change-Id: I7f75bf45089acaf1bd1b775351e05bcdcc89fc9e
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
The current scenario is as follows commit N with autorefresh
enabled and frame starts processing. On suspend commit N+1,
during virt_disable software resets CTL path after autorefresh
config is disabled. Since in hardware frame is still processing
sw reset is causing fifo underflow. This change waits for
vsync so that current autorefresh frame transaction completes
before issuing a CTL_SW_RESET.
Change-Id: Ib0662837e54b14cea6ab835a1093a2f048c473be
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
Add property to parse and select the ddr string based
on the detected ddr type.
Change-Id: I012b10e31a21a7a1a0e279df119e9803e2d5a0ce
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
This change fixes the 'commit 1aacef1e1d ("disp: msm:
sde: fix UBWC decoder version support for Kalama")'.
ubwc_ctrl must be set with global ubwc encoder version populated
from devicetree setting.
Change-Id: I85dc80e2e0436536a9b14e7e43199dc7b4421485
Signed-off-by: Yojana Juadi <quic_yjuadi@quicinc.com>
Signed-off-by: Gaurav LNU <quic_glnu@quicinc.com>
This change retrieves the dcwb_idx from hw_pp
to get proper hw block. The 'commit 6bb958c88b
("disp: msm: sde: fix dcwb idx selection for pp_dither
and CTL blocks")' has missed updating dcwb_idx in
cwb flush helper API while porting 'commit 85c5ca9790b3
("disp: msm: sde: fix dcwb idx selection for dither
and CTL blocks")'. Underruns are seen while configuring
cwb dither in mid tier targets as dcwb pp block counter
can be different.
Change-Id: Iaabbb5b3724592998894b88f36e19c978d3f8306
Signed-off-by: Gaurav LNU <quic_glnu@quicinc.com>
The dp driver inserts a failsafe mode to be in alginment with
DP specification.
This change ensures that the added failsafe mode does not
get filtered out when a specific mode is selected via
the debugfs functions.
Change-Id: I56039527eaf77111c6a51a40d1ea143fa0693a70
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
Update PHY settings for targets using pll-revision as
"4nm-v1".
Change-Id: I1242154cdb3aef5c9a84954d69e40f0520157620
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
Program the read pointer after configuring the tearcheck registers.
The read pointer register should be configured after VSYNC_COUNTER_EN
is set as per hw programming sequence.
Change-Id: Idc410867aa92760b43117552b00914481c0ba6d3
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Currently we are enabling all the lanes irrespective of the
lanes we are actually going to use. Add support to enable
only those lanes that are required and thus save power.
Change-Id: I9aae76eeaa05a79337d4e4b1f2e36ea9842bd580
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
Add check for READY state in dp_display_host_deinit.
Clear READY state in deinit flow to prevent state machine
errors with multiple concurrent plug/unplug events.
Change-Id: I0b17cffc7a3261ae4259225bb51452162763ae2a
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
Since PLL UNLOCK status bit is a sticky bit, ensure this bit
is cleared before unmasking PLL UNLOCK error.
Otherwise unnecessarily DSI controller will trigger error
interrupts for the stale status, the moment error is
unmasked.
Change-Id: I7b7aa63b5e508dde446a4469d9a6625a071dae00
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
Sixzonev2 uses a combination of broadcast enabled and disabled
cases to program luts and modify PA config registers respectively.
It also uses SB LUTDMA which requires all DSPP sub blocks to be
flushed. The modify operation can't be used with broadcast enabled and
was resetting the sub blocks to only indicate DSPP1 and causing the
DSPP_SB flush to be missed for DSPP 0. This change maintains the original
dspp indices to be used for broadcast enabled case and SB LUTDMA kickoff.
Change-Id: I1079878bbf44238419d4f88a40814e488c0800e3
Signed-off-by: Alisha Thapaliya <quic_athapali@quicinc.com>
Suppose there's a mode change in Nth commit and N+1th commit mode
change request for dynamic clock came even before the Nth commit
mode is set in DSI. Now, restoring the bit clock and porches during
mode set of Nth commit will update the clock and porches according
to the new dynamic clock request which should have actually been
handled in N+1th commit mode set and this can lead to DSI underflow
/overflow.
Avoid restoring bit clock during bridge enable as it is already
taken care during bridge mode fixup.
Change-Id: Ieecb0020a77f5e082a8b9da0ecf461acdbe89e0c
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
To set frequencies for link clks, the clk manager index of
ctrl is require. Use ctrl cell index to get clk manager index.
Change-Id: I175d0721e672fb4d368349584c8b448ba63f4224
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
In some corner cases there is pending vsync timestamp event to
sf when encoder is getting disabled. This is keeping vblank irq
to be enabled after sde_encoder_virt_reset leading to NULL ptr
access. In these cases, wait for vsync event to be completed which
disables the irq.
Change-Id: If0a6be1fc282906fb1b9c0fd18ede1d31d2549b3
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
Acquire mngr clk_mutex before updating link clock frequencies.
Failing this may lead to race around condition while setting the
link clock frequency rates.
Make sure byteclk and pclk rates of PLL are configured according
to clock manager and not the controller.
Change-Id: I2cd26e659ce166d5bc55eb6c060672eeee192bea
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
