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Merge "disp: msm: sde: parse ddr string based on detected ddr type"

qctecmdr 1 年之前
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45b0e9129e
共有 2 個文件被更改,包括 22 次插入4 次删除
  1. 15 2
      msm/sde/sde_crtc.c
  2. 7 2
      msm/sde/sde_hw_util.h

+ 15 - 2
msm/sde/sde_crtc.c

@@ -6583,6 +6583,8 @@ static void sde_crtc_install_perf_properties(struct sde_crtc *sde_crtc,
 static void sde_crtc_setup_capabilities_blob(struct sde_kms_info *info,
 		struct sde_mdss_cfg *catalog)
 {
+	enum sde_ddr_type ddr_type;
+
 	sde_kms_info_reset(info);
 
 	sde_kms_info_add_keyint(info, "hw_version", catalog->hw_rev);
@@ -6608,10 +6610,21 @@ static void sde_crtc_setup_capabilities_blob(struct sde_kms_info *info,
 				catalog->mdp[0].ubwc_swizzle);
 	}
 
-	if (of_fdt_get_ddrtype() == LP_DDR4_TYPE)
+	ddr_type = of_fdt_get_ddrtype();
+	switch (ddr_type) {
+	case LP_DDR4:
 		sde_kms_info_add_keystr(info, "DDR version", "DDR4");
-	else
+		break;
+	case LP_DDR5:
 		sde_kms_info_add_keystr(info, "DDR version", "DDR5");
+		break;
+	case LP_DDR5X:
+		sde_kms_info_add_keystr(info, "DDR version", "DDR5X");
+		break;
+	default:
+		SDE_INFO("ddr type : 0x%x not in list\n", ddr_type);
+		break;
+	}
 
 	if (sde_is_custom_client()) {
 		/* No support for SMART_DMA_V1 yet */

+ 7 - 2
msm/sde/sde_hw_util.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  */
 
@@ -16,7 +16,12 @@
 #define REG_MASK_SHIFT(n, shift)        ((REG_MASK(n)) << (shift))
 #define REG_MASK_ULL(n)                 ((BIT_ULL(n)) - 1)
 #define REG_MASK_SHIFT_ULL(n, shift)    ((REG_MASK_ULL(n)) << (shift))
-#define LP_DDR4_TYPE			0x7
+
+enum sde_ddr_type {
+	LP_DDR4 = 0x7,
+	LP_DDR5,
+	LP_DDR5X
+};
 
 struct sde_format_extended;