Graphe des révisions

2497 Révisions

Auteur SHA1 Message Date
Nilaan Gunabalachandran
3b303c57de disp: msm: sde: avoid mis-allocating dummy mixers
Dummy mixers for dedicated concurrent writeback can be allocated
as valid mixers. However, they should only be allocated for DCWB
usecases. Allocating these virtual resources incorrectly can lead
to underrun on external monitors. These dummy mixers should not
be tracked as available resources and exposed to dp for
mode validation.

Change-Id: I04f583d5b722e0a384a5446e3a8a2313a338aa12
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2021-09-09 09:48:08 -07:00
qctecmdr
f04eb4120c Merge "disp: msm: dp: use 3dmux when dsc is not available" 2021-09-07 07:12:22 -07:00
Samantha Tran
19979de0af disp: msm: sde: update IB vote to include AB factor
With this change, the IB vote will be based on the following:

IB = AB_aggregated / number of DDR Channels / DRAM efficiency factor

Number of DDR Channels and DRAM efficiency factor are now device tree
properties which can be modified and parsed at boot up.

Change-Id: I298043807150faec1cbc0d74eefcdd1a534b460a
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2021-09-02 21:04:40 -07:00
qctecmdr
6e4731175f Merge "disp: msm: avoid begin/end cpu_access calls based on dma-coherent attribute" 2021-09-02 14:49:31 -07:00
qctecmdr
f192f6d6dc Merge "disp: msm: dsi: reset the DSI command ctrl flags for every command" 2021-09-01 18:19:24 -07:00
qctecmdr
187dbfdc65 Merge "disp: msm: sde: allow spec fence signaled with PENDING_ERROR as non fatal" 2021-09-01 13:38:33 -07:00
Rajat Gupta
7f0f23c35f disp: msm: dp: fix to handle host ready failures
Handle host_ready failures and try to initialize host if not already.
Sometimes customizations for customers causes NOC error as host_ready
doesn't return early upon failure and the customer customization
tries to access aux register to reconfig upon aux failure while
reading EDID. Adding fix will make driver more robust to handle such
cases.

Change-Id: Ifa5c56daa32c4ef366a0e05718495ffcb40b96b3
Signed-off-by: Rajat Gupta <rajatgu@codeaurora.org>
Signed-off-by: Sandeep Gangadharaiah <sandgang@codeaurora.org>
2021-09-01 14:05:43 -04:00
Satya Rama Aditya Pinapala
b63a13c0b8 disp: msm: dsi: reset the DSI command ctrl flags for every command
The controller flags need to be reset for each command. On resetting
it only for a batch of commands, it may carry stale values and cause
unexpected behavior.

Change-Id: I8473be0c4361965a58c33a3d45420c533d48646b
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
2021-09-01 10:14:31 -07:00
Jayaprakash Madisetty
cc6122b749 disp: msm: sde: allow spec fence signaled with PENDING_ERROR as non fatal
In concurrent display usecases, dma_fence_array signaled op
can be called early which sets SIGNALED_BIT on spec fence, but
irq_dma_fence_array_work is not scheduled yet which clears the
PENDING_ERROR in dma_fence. Add changes to treat pending_error
with signaled cases as non fatal.

Change-Id: I3a59032345b8c6d1488e947e74985ed929112d1c
Signed-off-by: Jayaprakash Madisetty <jmadiset@codeaurora.org>
2021-08-31 14:18:43 -07:00
qctecmdr
63dc6b64c9 Merge "disp: msm: reset connector panel_dead during dsi bridge post disable" 2021-08-28 00:44:22 -07:00
qctecmdr
d4652960d6 Merge "Revert "disp: msm: dsi: allow cmd-engine enable/disable HW op at all times"" 2021-08-28 00:44:22 -07:00
qctecmdr
b8a102735a Merge "disp: msm: sde: Validate transaction counts for LUTDMA abs writes" 2021-08-27 21:23:19 -07:00
qctecmdr
419816332d Merge "disp: msm: sde: retry preclose commit in cases of -ERESTARTSYS" 2021-08-27 17:13:54 -07:00
Samantha Tran
9c771fe6e1 disp: msm: avoid begin/end cpu_access calls based on dma-coherent attribute
This change avoids unnecessary calls to dma_buf_end_cpu_access and
dma_buf_begin_cpu_access for context banks which have dma-coherent
attribute set.

Change-Id: I5120e55bed372d166d05da988714551428964b8b
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2021-08-27 09:48:45 -07:00
qctecmdr
e8a4a92814 Merge "disp: msm: dp: move fsa init from dp probe to dp hotplug" 2021-08-26 14:23:36 -07:00
Steve Cohen
1416e72e62 Revert "disp: msm: dsi: allow cmd-engine enable/disable HW op at all times"
This reverts commit 65f3cc37a4.

This change breaks TUI use-cases by allowing CMD engine to be
disabled on trusted VM without primary VM having knowledge of
this HW update.

Change-Id: Ieb67dc841299a149e9f1028fd8f98bd857f1f711
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2021-08-26 12:37:45 -04:00
Steve Cohen
b57a445cf4 Revert "disp: msm: dsi: skip DSI disable operations in trusted VM"
This reverts commit 61518d4f5f.

This change corrupts the DSI engine state machine which expects
all the state tracking updates from the calls that are now being
skipped.

Change-Id: I506ecbd98cc771950b17212a2702e7dde81fe539
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2021-08-26 12:35:38 -04:00
Vara Reddy
e0219f400c disp: msm: dp: move fsa init from dp probe to dp hotplug
DP driver, at probe time, checks for fsa probe completion by
registering a notifier callback. The fsa driver performs some
I2C operations at this time. But occasionally, it takes multiple
attempts to complete these I2C transactions,adding huge delays
to display driver probing.If this delay is long enough, then
display usermode services start before display driver probe completes
and as a result, it fails to enumerate any displays.

Since the fsa switch is needed only after an external display is hot
plugged,this change moves the fsa probe check to dp hotplug handler.

Change-Id: I1b592ec3921a0b406ca23142d07e1a7e8b72090e
Signed-off-by: Vara Reddy <varar@codeaurora.org>
2021-08-25 16:36:19 -07:00
Samantha Tran
e1cb09ad31 disp: msm: sde: retry preclose commit in cases of -ERESTARTSYS
This change allows the commit in preclose to be attempted a
number of times in the event that the return value is -ERESTARTSYS.
This can happen if there is some timing delay which is preventing
the commit to go through completely and an error code is returned.

Change-Id: I26d85d777be182bc153532d7c06f816c934783a4
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2021-08-25 13:42:59 -07:00
Samantha Tran
8dbb23a8f5 disp: msm: reset connector panel_dead during dsi bridge post disable
This change resets panel_dead property at the end of dsi bridge post disable.
Currently as part of the ESD recvoery sequence, dsi_bridge_enable resets this
property, but WD vsync source is selected before this point based on the older
panel_dead status. With this change, panel_dead will be in a proper state and
the correct vsync source will be selected during recovery.

Change-Id: I6d614113cfb0ae8a857974bb4d4f8ceb5988a0c8
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2021-08-24 13:32:04 -07:00
qctecmdr
3a2c526376 Merge "disp: msm: dsi: add submode argument to find correct mode" 2021-08-24 05:24:54 -07:00
qctecmdr
0f0c5990ca Merge "disp: msm: dsi: skip DSI disable operations in trusted VM" 2021-08-22 22:22:26 -07:00
qctecmdr
ce920f58ee Merge "disp: msm: sde: fix dsc initial line caluclation" 2021-08-20 20:19:52 -07:00
qctecmdr
829303e368 Merge "disp: msm: add look up table for dsc format specific rc params" 2021-08-20 17:08:06 -07:00
Steve Cohen
61518d4f5f disp: msm: dsi: skip DSI disable operations in trusted VM
Secondary VM will do a disable commit when transferring HW
ownership back to primary. This will end up disabling the CMD
engine before releasing HW back to primary VM. Primary is
unaware that the engine has been disabled and ends up in a
bad state until it gets re-enabled.

This issue was introduced by: commit 65f3cc3 (disp: msm: dsi:
allow cmd-engine enable/disable HW op at all times).

Fix the issue by ensuring CMD engine does not get turned off
in the display disable path for trusted VM.

Change-Id: I1638a181d136e18a836c3ba08daee1c5fcaa9de3
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2021-08-20 19:39:48 -04:00
qctecmdr
4f0632e798 Merge "disp: msm: dp: check for dp link clocks before accessing dp registers" 2021-08-20 11:01:30 -07:00
qctecmdr
19e36887d2 Merge "disp: msm: remove use of DMA attributes LLC_NWA and Upstream Hint" 2021-08-19 18:45:48 -07:00
Nilaan Gunabalachandran
d7172c5009 Revert "disp: msm: sde: program qseed through ahb"
This reverts commit 3617430855.
This change will re-enable qseed programming through lutdma.

Change-Id: I57b897088eeccddc63ee010e296b5d4622d27a9f
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2021-08-19 13:15:54 -07:00
Prabhanjan Kandula
d863e18638 disp: msm: sde: fix dsc initial line caluclation
Current DSC intial line calculation is giving extra line on top of
recommended value from systems since number of active soft slices
considered is wrong. Fix the number or usage of active soft slices
in an encoder to align dsc initial line with recommended setting.

Change-Id: I321260e22b7824b8c481a55b54831ce9535661cc
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
2021-08-19 11:48:52 -07:00
Prabhanjan Kandula
d5390da6c7 disp: msm: Update dsc 422 and 420 encoding settings
Update dsc configuration and pps programming for 422 and
420 encoding as per the DSC hardware spec.

Change-Id: I4251614cdcd550ed724b1d0dba4846cada4b5392
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
2021-08-19 11:47:34 -07:00
Prabhanjan Kandula
5ae2fa9ac8 disp: msm: add look up table for dsc format specific rc params
Current SDE driver computes rc parameters considering only bpp
and chroma format and its values do not match the recommended
settings. Add a look up table for these dsc encoder format
specific initial rate control settings.

Change-Id: Iff4cd0534618eb043351fd2a9c7759b8ee503f76
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
2021-08-19 11:09:06 -07:00
Prabhanjan Kandula
33e63e03c7 disp: msm: sde: unify dsc format index look up for tables
Simplify dsc encoding format index look up by clubbing
dsc v1.1 and v1.2 tables.

Change-Id: I145ff4e301758d2991ca992fc6616ed2e7b72754
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
2021-08-19 11:08:54 -07:00
Vara Reddy
c57fe2034a disp: msm: dp: check for dp link clocks before accessing dp registers
Add safety checks to check for dp link and core clocks before accessing
the main control registers during dp teardown or dp setup.

Change-Id: Ic80050b7c1cec59d7fc27a1c5f12fa1b244f86fb
Signed-off-by: Vara Reddy <varar@codeaurora.org>
2021-08-18 22:24:32 -07:00
qctecmdr
b6b3b01190 Merge "disp: msm: select non secure context bank regardless of dma buf flags" 2021-08-18 16:48:48 -07:00
qctecmdr
bb36f9fd40 Merge "disp: msm: sde: add helper to check VM hw availability" 2021-08-18 16:48:48 -07:00
qctecmdr
eeb3606b4c Merge "disp: msm: sde: correct rounded corner bottom start check" 2021-08-18 12:49:56 -07:00
Anjaneya Prasad Musunuri
a3f8e9ab8f disp: msm: sde: correct rounded corner bottom start check
Bottom start must be lesser than display height by at least
one line.

Change-Id: I36fbf68ee6733c020f235dca04c4b00c1e5a2312
Signed-off-by: Anjaneya Prasad Musunuri <aprasad@codeaurora.org>
2021-08-17 23:09:08 +05:30
Yashwanth
0ca8cea39e disp: msm: dsi: add submode argument to find correct mode
During DSC-NonDSC usecase, submode should be passed to
dsi_display_find_mode to differentiate between the modes
containing same timing info. This change adds submode
argument to find the correct mode in such cases.

Change-Id: I82284aeb9c3fd187c4f0961443dd1d0893a3c094
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2021-08-17 12:58:22 +05:30
Christopher Braga
43bfd9f435 disp: msm: sde: Validate transaction counts for LUTDMA abs writes
Existing LUTDMA hardware runs into issues when an odd number of
LUTDMA absolute address writes are executed before a GDSC power
collapse. Update LUTDMA logic to force absolute write payloads to
always contain an even number of writes.

Change-Id: I476feeab550f4b176d0adccaa5f2d38041e87657
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
2021-08-16 15:27:15 -04:00
Samantha Tran
2c2224bdf3 disp: msm: remove use of DMA attributes LLC_NWA and Upstream Hint
Remove DMA_ATTR_IOMMU_USE_LLC_NWA and DMA_ATTR_IOMMU_USE_UPSTREAM_HINT
attributes as they are no longer needed since io-coherency is enabled.
Passing this attribute is a no op since buffer is io-coherent and will
be mapped with a write allocate policy contradicting intention
of that attribute.

Change-Id: I882f148d770c795eb005c5391171a6280c083d37
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2021-08-16 12:00:33 -07:00
Krishna Manikandan
9f41ad11b3 disp: msm: sde: add null check for drm file in msm_release
Drm file is not set to NULL after freeing it from drm
release. This can result in use-after-free issues in
some scenarios. Add a mutex lock and other proper null
checks to prevent such issues.

Change-Id: Ic35b0a76166b0f47a354b1737e6f4c3ac1437ed4
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
2021-08-16 06:31:40 -07:00
qctecmdr
88877f3037 Merge "disp: msm: sde: add sde data to va minidumps" 2021-08-15 18:31:12 -07:00
qctecmdr
d55bc8d204 Merge "disp: msm: dsi: acquire panel lock for command transfer through debugfs" 2021-08-15 18:31:11 -07:00
qctecmdr
4ec64c1672 Merge "disp: msm: sde: compute timeouts based on refresh rate" 2021-08-13 20:50:46 -07:00
qctecmdr
4b778c82ce Merge "disp: msm: sde: update unmult offsets" 2021-08-13 20:50:46 -07:00
qctecmdr
c9fb272a73 Merge "disp: msm: dsi: allow cmd-engine enable/disable HW op at all times" 2021-08-13 20:50:45 -07:00
Satya Rama Aditya Pinapala
adfbc98df7 disp: msm: dsi: acquire panel lock for command transfer through debugfs
To ensure that no other command transfer is in progress, during DSI
TX operation through debugfs, panel lock needs to be acquired.

Change-Id: I8d3871e32277840867d9494720e77df3566e30d3
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
2021-08-13 13:18:44 -07:00
qctecmdr
7986d0d1b1 Merge "disp: msm: dp: add support for 3.75:1 compression" 2021-08-13 08:58:26 -07:00
Steve Cohen
7f3b2f0a4b disp: msm: sde: add helper to check VM hw availability
Add a utility function to check if HW has been handed over to
another VM.

Change-Id: Ic36ca1e7f15f7608e69d69fc3f4e7ad40be15704
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2021-08-12 22:58:30 -04:00
qctecmdr
7ec82f88a8 Merge "disp: msm: add qsync refresh rate support per mode" 2021-08-12 14:10:43 -07:00