Add the following Spectral scan capabilities at the pdev level.
a) Normal Spectral scan capability
b) Agile Spectral scan capability for 20/40/80 MHz
c) Agile Spectral scan capability for 160 MHz
d) Agile Spectral scan capability for 80+80 MHz
Also change the definition of existing Spectral scan capability
at psoc level.
CRs-Fixed: 2840144
Change-Id: I18be48ec4095fa29b62800a9df58b72295747547
Add a new WMI service bit to indicate whether normal
Spectral scan is disabled.
CRs-Fixed: 2840128
Change-Id: I09314afeb5372f83b8356e06f245c83c7acbc85d
Currently, Host driver assumes WMI_MIN_HEAD_ROOM is part of WMI
messages and Validations are done accordingly. But this
WMI_MIN_HEAD_ROOM is not considered in the firmware. Because of
this host may drop valid events.
To avoid this, Don't consider WMI_MIN_HEAD_ROOM while validating WMI
msg length.
Change-Id: I5f1fe12cfae570e636defb8a4a46ec154f988195
CRs-Fixed: 2844982
Currently DMA mask for the device is set during hif_enable_bus.
If the datapath memory prealloc feature is enabled, there are
a few dma memory allocation which is done before the DMA mask
is set for the device. This leads to the aforementioned dma
memory pre-allocation to be attempted at the default DMA mask.
Due to this the entire device capability of dma address might
not be used.
Add hif api to set dma mask before hif is initialized. This
is needed to set dma mask in case of datapath memory pre allocation.
Change-Id: I6fd25d9cb6ab3aaacd6f959abe4e060e23f37095
CRs-Fixed: 2845020
In existing implementation, for monitor mode below allocation
are done at pdev attach and init time.
a. 64 monitor buffer allocation for RxDMA monitor buffer ring
b. Link descriptor memory allocation for monitor link descriptor ring
This memory is waste of memory for customers not using monitor mode and
low memory profile.
To optimize this memory, allocate all buffers and link descriptor memory
at monitor vdev creation time.
Change-Id: I873c76d2f625a782532a101037915b0353928a5b
CRs-Fixed: 2829402
Use the hal_srng APIs that handle byte-order conversion of ring pointers
for big-endian platforms.
Change-Id: I2664636d5d2a1abfd7b643ea4c4d63d328a9880f
CRs-Fixed: 2845047
Current implementation of hal_srng_access_start() reads the ring pointer
in the same byte-order as it is written by the target. This results in
byte-order mismatch on a big-endian Host because the WLAN target is
little-endian based. For most of the srngs, the target already takes of
this by converting the ring pointer to the host-order before writing to the
DDR. But for other srngs, the Host needs to handle the endianness
conversions. Add HAL APIs to do the same.
CRs-Fixed: 2844519
Change-Id: Ieb47391ac0acc3724e854f433915dd5b1219bebe
In DFS, to check if a channel is radar, we use the flags that
are filled from UMAC to check for radar. Since the channel list
in UMAC are dynamically calculated, the dynamic flags will not be
consistent over multiple channel pointers.
Use the radar information in regulatory for individual subchannels
to check for radar in a given channel. Define these new APIs
under a feature specific macro.
Change-Id: I7f86560c3d29d2366c6506ccf63204263cbc0ef1
CRs-Fixed: 2841168
Swap each word of key_data before sending key install command.
This is needed since copy engine swap is enabled for big endian platform
and key needs to be plumbed in network byte order for decoding to happen
correctly.
Handle the swap in wmi layer since all other big endian conversions are
handled in this layer.
Change-Id: Ia6f0d579f3edaf32193c353ea2fe35cc40f55399
Replace pdev_id with mac_id for ucfg_dcs APIs and update
related documentation.
Change-Id: Ie0dbe992c113aac597dbb6820acd3faba3ac9f3c
CRs-Fixed: 2843510
rx_ring_history is an array of pointers, address of pointer is
always a non-NULL value, this always passed the NULL check,
which leads to NULL pointer dereference, fixing the same.
Change-Id: I401203a6f2a5930869cf4002ac0e714d3fdba62f
CRs-Fixed: 2844038
scenario:
FISA new FST entry is initialed, host will start one timer to
send HTT MSG DP_HTT_FST_CACHE_INVALIDATE_FULL to FW in 5 ms,
WOW suspending happened in the same time, PCIe bus get suspended.
5 ms later, HTT msg sending will try to prevent PCIe L1 to update
CE SRNG HP register, hit assert as PCIe bus suspended already.
suspend and cancel the FSE cache flushing timer when dp_bus_suspend,
resume it when dp_bus_resume.
CRs-Fixed: 2843214
Change-Id: Ie2bc115a0de068335d6c46749f52d205cc21f5a3
The response for the respective TWT operations can either be synchronous
or asynchronous (wherever specified). If synchronous, the response to
this operation is obtained in the corresponding vendor command reply to
the user space. For asynchronous case, the response is obtained as an
event with the same operation type.
Drivers shall support either of these modes but not both simultaneously.
The support for asynchronous mode is advertised through the new flag
QCA_WLAN_VENDOR_FEATURE_TWT_ASYNC_SUPPORT. If the driver does not
include this flag, it shall support synchronous mode.
Change-Id: I359e12c5147b0115158d03a7a08d74beca78455c
CRs-Fixed: 2842872
Define the following additional TWT operations:
QCA_WLAN_TWT_GET_STATS, QCA_WLAN_TWT_CLEAR_STATS,
QCA_WLAN_TWT_GET_CAPABILITIES, QCA_WLAN_TWT_SETUP_READY_NOTIFY.
Also define new attributes to qca_wlan_vendor_attr_twt_setup
and qca_wlan_vendor_attr_twt_nudge.
Change-Id: I687fd215c13aa12741d8ba7af23507f930d0ec81
CRs-Fixed: 2842072
Add support to configure minimum and maximum wake duration
values, minimum and maximum wake interval values for TWT setup.
Change-Id: I69c328815be511833abce0fcd18649e136027f53
CRs-Fixed: 2827115
Direct Buf Rx has a source ring to communicate with the target.
The target updates its tail pointer in little-endian format and this update
doesn't go through any byte-order conversion at the target. On a big-endian
Host platform, this tail pointer will be read in reverse order of bytes.
To fix this, convert the tail pointer to the Host order before using it.
Change-Id: Ibcaf3d7507910ea81eeb895772241ab9861ee45a
CRs-Fixed: 2843259
With current implementation host does not allow
6GHz AP for WPS security, add a change to allow 6GHz AP for WPS.
Change-Id: I9e330f2984a716bb56e47313b65eedb4a1a0e216
CRs-Fixed: 2814259
Do not allocate memory if the ask is larger than the
maximum memory allowed for malloc. We have it limited to 4MB.
CRs-Fixed: 2828104
Change-Id: I5b463dd8eb640c76882653e82e6f6db7cb651cf2
Currently, 6g PSC/non-PSC channels in the scan request are
scanned or optimized to scan only if RNR IE is found based on
the inis scan_mode_6ghz and scan_mode_6ghz_duty_cycle.
As scan_mode_6ghz_duty_cycle is set to 4 by default, first 3
scans are optimized to scan only if RNR IE is found and 4th scan
would be full scan. If there is any standalone AP in 6g channel
that doesn't advertize RNR IE in colocated APs beacons/probe
responses, that's not scanned till the 4th scan.
Reverse the order for scan_mode_6ghz_duty_cycle such that the
first scan of every four scans is a full scan and rest of the
three scans are optimized. So, the standalone 6g APs can be found
in first scan itself based on the ini scan_mode_6ghz.
Change-Id: Ice1614a94f1fd166e283355616ace241a5df2bcb
CRs-Fixed: 2829550
Add a boolean is_chan_hop_blocked in struct regulatory_channel to check
if a channel is blocked for ACS hopping, when the noise detection param
on that particular channel is above the threshold.
Change-Id: Id1c73f1b153d2064eaf3a72a21d14a6f63ad0de4
CRs-Fixed: 2837859
Account for the Tx buffers allocated for IPA during
init. Add this memory to the overall Tx nbuf memory
allocations. Ensure that the nbuf size is taken from
end pointer to head pointer of nbuf.
Change-Id: Ie3a46c7e7674f3f2e1bf9e0791a7eb53d4bb0b21
CRs-Fixed: 2831015
During TCP Tx traffic account for the Tx nbuf memory mapped
and unmapped in the driver.
Change-Id: I40df92f124eec94f2fa3ddc8bcd910615f4539bf
CRs-Fixed: 2831015
WLAN chip components are little-endian based. When such a chip is attached
to a big-endian Host platform, there will be a mismatch in the order of
bytes for the data that is transferred between the Host and target.
Spectral HW module transfers the Spectral report directly to the Host DDR.
This transfer doesn't go through any byte-order conversion at the HW side.
So, to avoid invalid reads at the Host side on a big-endian platform,
convert the Spectral report to the Host byte-order before using it.
Change-Id: I742537f3a95ffca2e12b83535e83e2870ad06b10
CRs-Fixed: 2838371
