Grafik Komit

563 Melakukan

Penulis SHA1 Pesan Tanggal
qctecmdr
389f327c0f Merge "msm:ipa: DDR to SRAM optimization for eth" 2021-05-05 15:47:03 -07:00
qctecmdr
5e63fdb447 Merge "msm: ipa: Enable GSI Channel almost empty Feature" 2021-05-05 15:11:15 -07:00
qctecmdr
432970c45d Merge "msm: ipa3: add ipa sw-flt functionality" 2021-05-05 09:51:12 -07:00
qctecmdr
6066a1fe88 Merge "ipa: Add debugfs for header table offsets" 2021-05-05 07:40:38 -07:00
Skylar Chang
6a4dff1d40 msm: ipa3: add ipa sw-flt functionality
Add sw-flt support to specify the mac,
ip segments and ifaces to route to SW-path.

Change-Id: I95afe23e9e335d3a55d7cb560e4e7d369f747688
Signed-off-by: Skylar Chang <chiaweic@codeaurora.org>
2021-05-05 04:11:44 -07:00
qctecmdr
1a6a777b9f Merge "ipa: Move kernel-tests from ip_accelerator to techpack." 2021-05-05 04:08:10 -07:00
qctecmdr
f8025918f9 Merge "ipa: Add ipanat library to the techpack." 2021-05-05 03:30:25 -07:00
Ilia Lin
e3ce2f25dc ipa: Add debugfs for header table offsets
Print used and free offset sizes in the header table debugfs

Change-Id: I56ab0a9f607dc45d3a83a4e3749370b02caf7a0a
Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
2021-05-05 10:28:42 +03:00
Ilia Lin
f1c1fb3a16 ipa: Move kernel-tests from ip_accelerator to techpack.
Move ip_accelerator which is a part of kernel-tests-internal
from kernel to techpack. Updated up to SHA1:
b8790774643dbfea5b312ed422ef86b54e4c8d7f

The kernel-test-module was moved into the driver,
and will be compiled as part of debug build.

Change-Id: I427b9ea061401c74845d2bd0d505da747d5fe89f
Acked-by: Eliad Ben Yishay <ebenyish@qti.qualcomm.com>
Signed-off-by: Amir Levy <alevy@codeaurora.org>
Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
2021-05-04 20:50:23 -07:00
Ilia Lin
5faad0ab9e ipa: Add ipanat library to the techpack.
Moving the ipanat library sources from the ipacm project to here.
The library will be compiled separately and will be common
for the ipacm and ipa-kernel-tests.

Change-Id: I01becf981e15ea0c2958423585ea487affb421d0
Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
2021-05-05 06:48:22 +03:00
qctecmdr
e7414c97c6 Merge "msm: ipa: add unit tests for NTN3 offload" 2021-05-04 19:03:59 -07:00
qctecmdr
52ccb99a40 Merge "msm: ipa: Workaround for MHI target" 2021-05-04 19:03:59 -07:00
qctecmdr
fbfd385847 Merge "ipa: Distribute header table on SRAM and DDR" 2021-05-04 09:14:06 -07:00
Ilia Lin
b9deeaa3dc ipa: Distribute header table on SRAM and DDR
Use both local (SRAM) and system (DDR) memory
to allocate headers for further insertion.
QMAP headers and partial headers from clients
will be placed in the DDR.
Full headers from clients will be placed
in the SRAM as long as there is enough space.
Once the SRAM buffer runs out of space,
all new headers will go to the DDR.


Change-Id: Ic3913bc1eac4b8629b52c5cdbab1d144bfda776e
Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
2021-05-04 13:31:48 +03:00
qctecmdr
0cd381f7f7 Merge "msm: ipa: fix wrong check for debugfs on IPA GSB" 2021-05-04 02:29:40 -07:00
Chaitanya Pratapa
6415d1f62b msm: ipa: fix stats dump
Make changes to fix the stats collection.

Change-Id: Ib8ea3ca44951186ec472578fd13218bbc8c0120c
Signed-off-by: Chaitanya Pratapa <cpratapa@codeaurora.org>
2021-05-03 11:30:33 -07:00
qctecmdr
df3971e891 Merge "ipa: Dynamic move of filter rules between DDR & SRAM" 2021-05-02 07:29:04 -07:00
Sivan Reinstein
31104f6f79 ipa: Dynamic move of filter rules between DDR & SRAM
Allow moving of Non-Hash filter rules tables between
DDR memory and SRAM memory dynamically based on
table size and SRAM storage availability.

Change-Id: I8ff710e35be9ee1e7bb026fa7fda75a17200914c
Acked-by: Nadav Levintov <nadavl@qti.qualcomm.com>
Signed-off-by: Sivan Reinstein <sivanr@codeaurora.org>
2021-05-02 08:44:51 +03:00
qctecmdr
7b2c2c8683 Merge "msm: ipa: Add wrb_mod_threshold to AQC evt scratch" 2021-04-29 19:12:01 -07:00
Bojun Pan
5ad90dcb6e msm: ipa: Enable GSI Channel almost empty Feature
Enable GSI Channel almost empty Feature for MHI DL channel.

Change-Id: I9e27044f30bf61b91c0dcd7b7f109404b303bb62
2021-04-29 18:33:35 -07:00
Bojun Pan
48672431e8 msm: ipa: fix wrong check for debugfs on IPA GSB
The return for debugfs API got changed. The fix here is to fix the
return check for IPA GSB debugfs init.

Change-Id: I4c6e97c612592763ceab66abdee99d7761c9c164
2021-04-29 15:42:44 -07:00
qctecmdr
6c843a50bf Merge "msm: ipa: update IPA SRAM mapping" 2021-04-29 15:10:01 -07:00
qctecmdr
7abf7544dd Merge "ipa: Fix Test HW mode handling" 2021-04-29 11:21:43 -07:00
qctecmdr
2e1ff23596 Merge "msm: gsi: add gsi profiling stats and fw version to debugfs" 2021-04-29 06:50:15 -07:00
Ilia Lin
4fdf719c72 ipa: Fix Test HW mode handling
Operate the clocks in the test HW mode in the same way
as in normal HW mode.

Change-Id: I58f64e7737bf8310156ac47837eb79c91a747e97
Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
2021-04-29 14:11:03 +03:00
qctecmdr
ad7cae101a Merge "msm: ipa: GSB support" 2021-04-29 00:59:49 -07:00
qctecmdr
f80ed986e4 Merge "msm: ipa: update the rule priority" 2021-04-29 00:08:52 -07:00
Sivan Reinstein
d1dfec34da msm: gsi: add gsi profiling stats and fw version to debugfs
Add GSI profiling stats data and the GSI FW version to debug fs.

Change-Id: I5749339f5ec9656e636a512668025bb09a97a3ec
Acked-by: Nadav Levintov <nadavl@qti.qualcomm.com>
Signed-off-by: Sivan Reinstein <sivanr@codeaurora.org>
2021-04-29 09:39:20 +03:00
Amir Levy
3a5b18e7be msm: ipa: Add wrb_mod_threshold to AQC evt scratch
Add AQC head_ptr_wrb_mod_threshold to gsi event scratch
and configure according to required value.

Change-Id: Ie1234d76b20fe9e17d5a0a295f748a5876ef4ddd
Signed-off-by: Amir Levy <alevy@codeaurora.org>
2021-04-29 08:51:07 +03:00
qctecmdr
53ed770d59 Merge "msm: ipa5: check if the default channel is already tore down" 2021-04-28 19:52:18 -07:00
Bojun Pan
c42d56691f msm: ipa: Workaround for MHI target
Remove the gsi type pending irq check for MHI target.
We observe the HW generating the pending IEOB irq for DMA SYNC channel
as well as MHI UL channel.

Change-Id: Ib578e3e7fcf58e7cc20501994a35f14d98eda1b6
2021-04-28 16:49:13 -07:00
Bojun Pan
76a366567e msm: ipa: update the rule priority
Correct the rule priority for IPA5.0.

Change-Id: Iff84c41d1def9b85d221f2fba03d52024ab9b000
2021-04-28 16:44:51 -07:00
Bojun Pan
63287fc3fe msm: ipa: GSB support
Add ODU pipe for GSB support.

Change-Id: I0379ce7e5d4cbd4c6066e5288a373006eb81e2f3
2021-04-28 12:36:20 -07:00
qctecmdr
450cdebeab Merge "ipa: Change IPA EP 34 GSI channel allocation" 2021-04-28 07:04:40 -07:00
qctecmdr
8060032166 Merge "msm: ipa: fix null pointer exception in rmnet_ipa" 2021-04-28 06:14:40 -07:00
qctecmdr
42c809b7b5 Merge "ipa: Move FLT rules to SRAM for ETH PROD client" 2021-04-28 04:28:38 -07:00
qctecmdr
62e9bc1275 Merge "ipa: Update SRAM partitioning for IPA5.0" 2021-04-28 03:39:14 -07:00
Amir Levy
a348c2498b msm: ipa: update IPA SRAM mapping
Update IPA SRAM mapping to accommodate with RQoS Q6
changes. Modem memory is increased and NAT table moved
after modem memory to allow it to expend once needed.

Change-Id: I803693f2a337abb2f7219e6de48d25a57111df5b
Signed-off-by: Amir Levy <alevy@codeaurora.org>
2021-04-28 13:25:47 +03:00
Chaitanya Pratapa
16e202768d msm: ipa: fix null pointer exception in rmnet_ipa
Make changes to check if rmnet_ipa3_ctx is non null before
accessing it.

Change-Id: I26286cb43c2a116d78fbc072291454cc43e02ee5
Signed-off-by: Chaitanya Pratapa <cpratapa@codeaurora.org>
2021-04-27 23:25:49 -07:00
Michael Adisumarta
332e9a23de msm: ipa5: check if the default channel is already tore down
Stop only coalescing pipe if default pipe is not valid or
already tore down.

Change-Id: I9a6f65840bd6bbbb0e302d0d2c048a3e58fc88e1
Signed-off-by: Michael Adisumarta <madiusma@codeaurora.org>
2021-04-27 15:35:31 -07:00
Chaitanya Pratapa
5ad7dff0bc msm: ipa: page pool recycling enhancements
Added the following enhancements to page pool recycling logic.
1) Updated page pool implementation to use list instead of array.
2) Added provision to check for configurable number of list
elements when checking for free pages.

Change-Id: I01c43be5a169c1438fb29b8179854985e199d055
Signed-off-by: Chaitanya Pratapa <cpratapa@codeaurora.org>
2021-04-27 10:44:05 -07:00
Ilia Lin
b107cbe836 ipa: Change IPA EP 34 GSI channel allocation
Change IPA EP 34 GSI channel allocation to channel 8,
as per the latest EP configuration table.

Change-Id: I993c799429555d29120b8181f3d10140ce0c68cf
Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
2021-04-27 16:54:36 +03:00
Sivan Reinstein
ff5fa36289 ipa: Move FLT rules to SRAM for ETH PROD client
Move Non-Hash FLT table for ETH PROD client to SRAM

Change-Id: I03aeb0669ca54bc09f880f2ddfed97d540385a00
Acked-by: Nadav Levintov <nadavl@qti.qualcomm.com>
Signed-off-by: Sivan Reinstein <sivanr@codeaurora.org>
2021-04-27 11:15:21 +03:00
Sivan Reinstein
a33e546e48 ipa: Update SRAM partitioning for IPA5.0
Update SRAM partitioning for IPA5.0 to support
Non-Hash IPv4 and IPv6 filtering rules tables in SRAM
In addition, seperate IPA5.0 and IPA5.1 SRAM partitioning.

Change-Id: I1c11212b0bb86305cd84e447eefbbf6d8f253cc0
Acked-by: Nadav Levintov <nadavl@qti.qualcomm.com>
Signed-off-by: Sivan Reinstein <sivanr@codeaurora.org>
2021-04-27 11:15:15 +03:00
Skylar Chang
90b154b71b msm:ipa: DDR to SRAM optimization for eth
1. Move default rule to hashable.
2. Move empty flt/rt table to SRAM location.

Change-Id: Ic77eecb56bd8808b8e5411cb27acaeae6f7c320a
2021-04-26 16:53:31 -07:00
qctecmdr
e0364fbb38 Merge "msm: ipa3: Remove ep suspend during usb resume." 2021-04-22 22:56:33 -07:00
qctecmdr
ee7a175c69 Merge "msm: ipa: APQ related fixes" 2021-04-22 19:30:43 -07:00
qctecmdr
bb51a5e7a5 Merge "msm: ipa3: add modem BW voting change support" 2021-04-22 17:47:20 -07:00
Michael Adisumarta
ff7b2ecc15 msm: ipa: rate limiting the warning
Rate limitting the warning if client doesn't have
callback.

Change-Id: I09b02181e4c34ecf342e150de76eace9341a0c0a
Signed-off-by: Michael Adisumarta <madisuma@codeaurora.org>
2021-04-20 22:39:40 -07:00
Piyush Dhyani
5cda42ee08 msm: ipa3: Remove ep suspend during usb resume.
With unified API changes, on usb channel during
resume ep suspend bit was not cleared which was set
during suspend channel. Now Removing ep suspend bit
while resuming channel.

Change-Id: Ib165299ac67d05139c7a964ac3464663d61260a1
Signed-off-by: Piyush Dhyani <pdhyani@codeaurora.org>
2021-04-20 14:41:01 +05:30