This change checks for the atomic state and ensures
that allocation and deallocation of vcpi slots is
prevented in the same phase.
Change-Id: I05c87db43eca8ba749ed8a0907dcaf95945dd645
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
Add a read only debugfs node to get current uidle status.
Usage:
cat /sys/kernel/debug/dri/0/debug/core_perf/uidle_status
N: indicate uidle is disabled.
Y: indicate uidle is enabled.
Change-Id: I7f28b406588c19decc4efc9012f5bac63925618a
Signed-off-by: Lei Chen <quic_chenlei@quicinc.com>
Currently, only rc ram is programmed through lut dma and
rc config is programmed through ahb.
This change programs both rc config and rc ram through lut dma.
Change-Id: I50a6e87dfbadb9c4a93cebdaa1e813f5be9ba5f5
Signed-off-by: Saurabh Yadav <quic_sauyad@quicinc.com>
In dual display configuration, where only one display is active at a time,
dsi0 and dsi1 can be used to drive primary large display and, one of the
dsi (dsi0 or dsi1) can be used to drive secondary display. This helps to
time division multiplex shared DSI for primary and secondary panel which
solves the bandwidth limitation problem. This change adds support to allow
sharing of dsi ctrl and phy between dual displays.
Change-Id: Ib4ed1bf51f587b544ec24b1b558ff83225b36e4b
Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
The clk_ctrl_cb and post_cmd_tx_workq callbacks are assigned
to individual ctrl during display bind. In case of dual display
with shared DSI, where primary display has ctrl0 & ctrl1 and
secondary display has ctrl1, the callbacks of ctrl1 of the
primary display gets overwritten with the callbacks of ctrl1
of the secondary display.
In the shared DSI design, only one display will be active at
a time. So, move the callback assignment of clk_ctrl_cb and
post_cmd_tx_workq to display prepare to fix this.
Change-Id: Ic02fa2f00c430fd5759400e06d82d004d4f7cba4
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
For usecase with S2-only or TVM buffers, the mapping needs to be done
after the SCM call. This is required to ensure the mapping is done to
the correct SID. Previously with S2-only usecase, the map was returning
the PA which would remain the same, so there were no issues even though
the map sequence was incorrect. But this sequence will cause issues with
CSF-2.5 as it uses 2-stage with TVM, and requires the mapping to be done
after the scm-call. Fix the sequence for legacy secure-camera preview,
legacy secure-display and CSF 2.5 solution.
Change-Id: Id663d30fdbf8725f43f61e67d2d7ce72aa9f9506
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Stop forcing max supported bpp to 24 in MST usecases.
Revert of I5b0e6ad86df39915073f469ea67e6addea165965.
Change-Id: Ibaa55952eeb6130afcb72910ad498f44d9aca9b1
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
For a HBR2 dongle, limit mode clock to ensure only resolutions
under 4k@30fps are supported on each port for MST usecases.
This fixes functionality with dongles which only support HDMI 1.4,
but don't filter out higher unsupported resolutions.
Change-Id: I2f9e53e55a31ede7fa891f29b9e7d36e108d375c
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
The height and width of ROI alignment must be integral multiple of
DSC slice height and width.
Add a check in partial update DT parsing function and disable
patrial update when panel ROI alignment can't match DSC slice
settings.
Change-Id: Ib80ca1cde5041936f9525e19757e95ff5898137f
Signed-off-by: Lei Chen <quic_chenlei@quicinc.com>
In some vm transitions, pp work might get executed on event thread
after handoff is completed on commit thread leading to crash.
This change flushes the pp event thread queue during vm pre-release
before lending the io resources to the other vm.
Change-Id: I53b76e48bc15084aa5519409fae0e692f49e7558
Signed-off-by: Saurabh Yadav <quic_sauyad@quicinc.com>
Signed-off-by: Lakshmi Narayana Kalavala <quic_lkalaval@quicinc.com>
-Add support to display-drivers modules using DDK framework for pineapple.
-Add macro that makes it easy to register new modules.
Change-Id: Id9cc0f367cff5b95b526fb42193471b3f3abd012
Signed-off-by: Varsha Suresh <quic_varssure@quicinc.com>
This change adds the check for hardware ownership before
reading the histogram statistics.
Change-Id: I0f811cef327c1dea9fb132d5fffd8da445e9d73f
Signed-off-by: Lakshmi Narayana Kalavala <quic_lkalaval@quicinc.com>
During cwb disable, encoder reset should be invoked to clean up
and release hw resources. This encoder reset should happen even
if cwb encoder TX_DONE is not successful to avoid rm rsvp leak.
Change-Id: I81353f19b69cb68d71f7d5b6477e37b6dab3ae00
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
In the case that the hw-fence feature is enabled in the display driver dt
but disabled during initialization by the display driver when hw-fence
driver dependency is disabled, the existing check to determine
if the function pointer is available is not sufficient to determine
if the feature is enabled. This change adds an additional check to ensure
we do not set the output-fences sw-override unless hw-fencing is enabled.
Change-Id: I7f5000037e7b2a142224ef9c45b383e5c701350a
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
In back to back partial update cases with CWB the CROP
registers are not reset causing WB timeout in the
following sequence-
1) Nth commit WB_roi != LM_PU_roi, WB CROP registers
are programmed.
2) N+1th commit WB_roi == LM_PU_roi, WB CROP registers
are not cleared retaining old values.
Clear the WB CROP registers in the second case to fix
the issue.
Change-Id: If09a697f48ecaf5ee08d6313be444748d048b20d
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
The inactive simulated DP MST connectors will not have a panel assigned.
So, the driver needs check for a valid panel before dereferencing the
panel object.
Change-Id: I60a4ca666f3c7c81a4e92e08cf572d5abac4ee78
Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com>
The dp_display_disconnect_sync is disabling the aux switch during
the attention hpd low processing. Ideally, the aux switch needs to
be turned off only when the dp cable is disconnected. With aux switch
getting turned off even while cable is connected is leading to HDCP
compliance test failure. This change will turn off aux switch only
when the cable is disconnected. It reverts the commit id
b6466ca7f597396cd2ecb3623d059435dfb0e4c6.
Change-Id: I90cc5f31b2be1afda61f74ea4e0a44332811ead3
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
Signed-off-by: Andrew Bartfeld <quic_abartfel@quicinc.com>
Current implementation we apply the color properties when atomic begin
is called and mark features as dirty if crtc is not enabled.
For some of the non double buffered features in video mode we will
see a corruption. Change removes marking color properties as dirty
based on crtc on/off.
Change-Id: I4d93b14627d2bc06fcbca3ea9538a4baedb00e56
Signed-off-by: Lakshmi Narayana Kalavala <quic_lkalaval@quicinc.com>
As we are merging upstream patches, resolve conflicts of namespaces in
downstream modules.
Change-Id: Id3af0de7102ddd92e312cb3cca10db9968974bcd
Signed-off-by: Prakruthi Deepak Heragu <quic_pheragu@quicinc.com>
Signed-off-by: Raviteja Tamatam<quic_travitej@quicinc.com>
Wait for the userspace to disable DP when usb cable is removed
during DP simulation. The usb notifier is a blocking call.
Change-Id: I6c00cc684b4d99da30a129f034eb17bf505738bb
Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com>
When broadcast command is sent with command DMA window scheduling enabled,
DSI_TRIG_CTRL.COMMAND_MODE_DMA_TRG_MUX does not get reset after command
transfer. Due to this next unicast command on slave fails.
This change resets DMA trigger mux during DSI_TRIG_CTRL initialization.
Change-Id: I74503d82ab1cb6ca4d61a9d14f2b3cd2c3936ea7
Signed-off-by: Kashish Jain <quic_kashjain@quicinc.com>
In DMA start window scheduling, TRIG_CTRL.COMMAND_MODE_DMA_TRIGGER_SEL
is programmed to SW + DMA start window trigger. But if DMS switch
comes after command is scheduled, COMMAND_MODE_DMA_TRIGGER_SEL gets
reprogrammed to SW trigger leading to command transfer failure.
Program the COMMAND_MODE_DMA_TRIGGER_SEL only from the CMD DMA Tx path.
Change-Id: I01062497bb70aa5fdcb25be3715c7cbc4c68b681
Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com>
Signed-off-by: Kirill Shpin <quic_kshpin@quicinc.com>
In MST atomic check function, allow to release vcpi slots for
any case of changes in modes, active state or connectors for a crtc state.
This reverts the commmit id 28cde80bd3666b6b339a21cac3d04b3b11c318b6.
Change-Id: Ice13790f2e652b336619e1d78b42ddb708b4cb2e
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
Attach the S2-only secure camera preview buffers with dummy drm
device during dma_buf_attach. This will ensure when sg_dma_address
will return the phys address for this buffer as its not backed
by a context-bank.
Change-Id: Iafd40352b92b842d19194976fa4b58e1e07e6f0d
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
When a display is disabled, the mst slot payloads get updated in the
topology manager and also the start_slot for the remaining payloads
get adjusted, if necessary to start from 1. But the copy of these
values in dp_mst_drm context are getting readjusted properly. But
since the local context is used to update the slot configuration in
the dp controller, it is possible for the slot configuration in the
source and sink to mismatch causing blank output.
This change introduces a 2 pass solution while updating timeslots to
make sure the values in the bridge context reflect the values in
the topology manager.
Change-Id: Ia6f66e8d5ffcde3f25b1b2649733a547a06de995
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
This is a partial revert of I67ace5c064b2b56d03732a78f334ea6b1b649608 which tries
to enable Sink CRC irrespective of the sink's CRC capability to workaround an
issue with a specific sinks which reports incorrect capability on first plugin.
But this causes some MST dongles to misbehave causing one or both outputs to
be blank.
Change-Id: I70c70db8ac371fe0094a45780216a2518d688a36
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
