Add display config support for compilation on neo target.
Change-Id: Ia2b9b8b76f833e233a8bf801485c6dd2104e1700
Signed-off-by: Karthik Andhavarapu <quic_kartkart@quicinc.com>
If MST is enabled, the controller needs MST ACT to be
completed to successfully transition to 'Ready for Video'
state. The driver is sending ACT during the normal flow
when transitioning from link training to stream enable.
But it is not sending ACT, if a link maintenance is
triggered after stream enable. This change adds the ACT
update to the link maintenance call flow.
Change-Id: I7aea53a1e54202f1d9059a8eb59f01fa97fe9eb9
Signed-off-by: Sandeep Gangadharaiah <sandgang@codeaurora.org>
In split link usecase with single DSI and dual sublink, the
pixel clock rate should be calculated based on effective lanes
rather than cumulative lanes on that DSI PHY. This effective lanes
can be expressed as number of lanes being used per sublink.
Change-Id: Ia534e816cc64b62c5fe0b9fcaabb9ba52d05bab0
Signed-off-by: Shashank Babu Chinta Venkata <sbchin@codeaurora.org>
This change moves TVM related code under SDE VM config.
Change-Id: I8357d6a984fd97f18f24eee33464299e8ea66b12
Signed-off-by: Andhavarapu Karthik <quic_kartkart@quicinc.com>
Currently RSC timer register programming is optimized for updating
only during timing param changes and not during RSC state changes
with same timing. Static wakeup time computation should consider
panel jitter for RSC clk state too, else it can result in RSC hang.
This change also removes extra logic for video mode prefil lines
computation for rsc config as video mode does not enable RSC solver.
Current issue scenario exposing the hang is in dual dsi display scenario
where RSC is in clock state and static wakeup time is programmed by
not considering panel jitter, after suspend/pmsuspend while waking up
if RSC switches to command state if primary enabled first and vsync
may arrive much early based on the panel jitter. RSC hw can not handle
if TE arrives earlier than static wakeup time causing RSC hang.
Change-Id: I1434fdd71eb04fdbe22b3601500493c818e9126d
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
After an ESD failure, the PHY lanes and controller can be stuck in
an unknown state. This can result in interrupt storms and watchdog
failures, if these error states are not handled correctly. The following
change implements the below mechanism to avoid failures.
1) Disable error interrupts during an ESD reg read, which are re-enabled once
ESD check is successful.
2) On ESD failure, before turning off LP clocks, reset the PHY lanes and DSI
controller.
3) After the HS clocks are turned off, issue a PHY hard reset.
4) Before enabling/disabling error interrupts, clear the error status registers
as they are not cleared as part of controller reset.
Change-Id: If10e4edf095a334a9416d109ec4b1401d1a84505
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Limit dma read commands to sublink 0 in split link
configuration since all panels do not support read
on sublink 1.
Change-Id: I537abafc02afe1c3306175ac850f4f080154f443
Signed-off-by: Shashank Babu Chinta Venkata <sbchin@codeaurora.org>
Access file private data structures inside the
mutex lock only to avoid use-after-free issues.
Change-Id: If70731f517bcb47d4515f131fecafe702064cb45
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
When switching between 2 dongles/adapters it is possible
to have the same resolution with different link configuration.
Even though the pixel clock could be the same on replug, the
vco clock could be different depending on the link
configuration. Since the dp driver only exposes limited clocks
to the clock framework, in this specific scenario, the clock
driver is unable to recognize the change in source clock rate
and ends up skipping the clock reconfiguration.
This change adds support to park the pixel clocks on disable,
thereby forcing a reconfiguration on subsequent replug even
if the pixel clocks are the same.
Change-Id: If90b37d6285f6cad23cf1c11a7d6ccd6b4cf850c
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
The divider value for vco clock is only dependent on the link rate
and is known during pll configure. Instead of depending on the
clock framework to program this divider as part of stream clock
enable, this change moves the configuration to pll configuration
and removes the set rate call on the vco clock.
Change-Id: If687a8ab057fdfd6c3b3ad2bd1c51663d9182ff4
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Add a null check to avoid null pointer access while getting
pointer to sde_kms.
Change-Id: I00f77e2a5bf63217fa57408ee5ac238dcac3fb03
Signed-off-by: Samantha Tran <samtran@quicinc.com>
When sde_crtc_atomic_begin is called before crtc is enabled, all the
color processing features need to be moved from active_list to
dirty_list after sde_cp_crtc_apply_properties(). However, the
ltm_hist_en flag doesn't need to be set to false in this case.
Setting ltm_hist_en to false in this case will result LTM merge_en bit
being cleared incorrectly. This change replaces sde_cp_crtc_suspend()
with a new function that only updates the color processing feature lists
in sde_crtc_atomic_begin().
Change-Id: I75d7874899838855bda05a1e8eca0cb9523417e9
Signed-off-by: Ping Li <pingli@quicinc.com>
Disable vsync counter before single buffer tear check
update. It allows to trigger the resolution switch
frame as posted start frame.
Change-Id: I2726372fd0e6d14ab0f79e3e3b0731a074158682
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
On an MST unplug, the MST topology manager state needs to be cleared
so it can properly destroy the current topology. But since the mst
active state is cleared prematurely in the driver, this call is
skipped and on a subsequent plug-in, the topology manager ends up
using stale topology from previous configuration. Incorrect RAD
values are used for sideband, causing them to fail.
This change fixes the order of operations, so the topology manager
state is properly updated on unplug. It also removes a duplicate
hpd notification to usermode.
Change-Id: Idcff17be113a361a0b58e54d85957f30d1d4e2d6
Signed-off-by: Sandeep Gangadharaiah <sandgang@codeaurora.org>
Move thread priority call to kernel worker thread because
component bind API may run from vendor_modeprobe process
context when all drivers probe succeed. Thread priority
update is not allowed from vendor_modeprobe process
context.
Change-Id: Iafac97ce02942d6a2134495232f3c395ba4a362f
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Currently the bit clk rate is overridden by cached clock rate
even in dynamic clock disabled usecase where it is not configured.
Avoid this override by retaining calculated bit clock rate for respective
mode in such usecase.
Change-Id: Ib159219fd50ab977edb8332c83bc8b34aee2dc0f
Signed-off-by: Shashank Babu Chinta Venkata <sbchin@codeaurora.org>
On reclaim error, mem handle is still valid and reclaim
should be retried on next commit. This change keeps the
mem_handle valid.
Change-Id: Ie3e0cc3d37c7f1f260a7655f48a6aadece65a1ca
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Alter allocation method from kzalloc to kvzalloc since virtually
contiguous allocation should suffice requirement. This will avoid
unnecessary invocation of OOO handlers.
Change-Id: I8291ddae08f6427478cdd9b88d6148e02d7ab002
Signed-off-by: Shashank Babu Chinta Venkata <sbchin@codeaurora.org>
Reset feature wrappers of Rounded corner, Demura and SPR
based on display processing engine capabilities of target.
Change-Id: I0db1f23a1b8b81eb7867680930168e2c3a6999b9
Signed-off-by: Anjaneya Prasad Musunuri <aprasad@codeaurora.org>
When validating panel resource, no need to check reset gpio if using
ext bridge mode.
Change-Id: Id0df84b9e0d8b10f4dd6851d5b3ab31b220f8622
Signed-off-by: Yu Wu <zwy@codeaurora.org>
Commit b67da33a6307 ("trigger tx_wait if panel
resolution switch") increases the mode switch latency.
Alternatively, single buffer tear check registers can be
updated when vsync_in is disabled. It allows mode switch
frame trigger as posted start frame trigger.
Change-Id: I8068736b2ea01f6e4160e765fc39d7fc2a8590c9
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
