Commit Graph

22 次程式碼提交

作者 SHA1 備註 提交日期
Chaithanya Garrepalli
41fda10bc5 qcacmn: In WBM err process read peer_id from peer_meta_data
In WBM error processing read peer_id from peer_meta_data
instead of sw_peer_id.

This changes is needed because we need to process Rx packet
on ML peer. But in MLO case sw_peer_id field contains
link_peer_id where as peer_meta_data has ml_peer_id.

Change-Id: I3f469adfdf7efa88cb081e94fa9fe0c54c1fb078
2021-11-12 04:46:16 -08:00
Chaithanya Garrepalli
7ccb73b31f qcacmn: Add support for beryllium on WIN
Add support for split between lithium and beryllium
HAL files.
Add Wkk TLV support.

Change-Id: I7135e4061a4c3605d76c70c33320cbd533ea0c62
2021-08-13 12:04:12 -07:00
Chaithanya Garrepalli
f79a68f685 qcacmn: Fix lithium HAL generic APIs
HAL generic APIs which use HW definitons that
do not have same value across all lithium chipset
are moved to header files. So that these will be
compiled with appropriate header files

Change-Id: I6c167afa4212c5e884f5e18ff1ccb3bbbba8f5f5
2021-07-01 09:06:06 -07:00
Rakesh Pillai
47af4d320f qcacmn: Move to index based assignment for srng register offset
Currently the hardware srng register offset is statically
assigned to the handle. This can lead to incorrect index access
when targets (eg: wcn7850) is added which require additional
register offsets to be stored in the hw srng register offset table.

Move to the index based assignment of the srng register offset.

Change-Id: I8e38bdd0c28068029a0267fce706edf4378b9df8
CRs-Fixed: 2965081
2021-06-30 13:47:57 -07:00
nobelj
25acb759bf qcacmn: Fixes to enable LI & BE in a build
Changes to build Lithium and Beryllium together.
This is needed for WIN

Change-Id: I74c86803ea99fb17d1f73e8b9c4e7cf59751a707
2021-06-07 01:51:15 -07:00
Rakesh Pillai
59ea466ca4 qcacmn: Add HAL APIs for Lithium targets
Add hal soc API handlers for existing Lithium targets.

Change-Id: I2ca25c94702759eb8329eb24048c9f5732caa3cc
CRs-Fixed: 2891049
2021-06-05 15:10:50 -07:00
Mohit Khanna
4e6a7cf1bf qcacmn: Use function to attach HAL TX/RX ops
Assign th HAL TX/RX ops in a function instead of assining a structure
directly. This can be later extended to have default ops for a family of
chips and then override that with chip specific ops.

This also helps the case where a new hal_soc->ops needs to be added.
The new 'op' will need to be added to only a default ops initializer
(with assumption that it applies to all chips).

Change-Id: Iefa23d14110fa5252444fad89737a3b2b2fbab6f
CRs-Fixed: 2891049
2021-06-05 15:10:50 -07:00
Rakesh Pillai
783f811315 qcacmn: Send ring sel cfg to configure rx pkt tlvs offset
Currently the FW configures the mac with appropriate
offsets for rx pkt tlvs using the structure defined in
te FW and the host does not send the ring selction config
HTT message. This can create a problem when FW stops subscribing
to tlvs or changes its rx pkt tlvs offset.

Fix this by configuring the rx pkt tlv offsets via HTT
ring selection config message.

Change-Id: I1a2865f91b34dd7bda1af8651d7831097dac0bee
CRs-Fixed: 2860504
2021-01-29 00:04:19 -08:00
Dustin Newman
2d1625aabe qcacmn: hal: Initialize hal_hw_txrx_ops for 5018
Change hal_hw_txrx_ops struct to designated initializer syntax for
structs for 5018.

Change-Id: Ie04dc1ebaa4e4964a565416c900c55e309638261
CRs-Fixed: 2837917
2021-01-11 04:06:52 -08:00
Saket Jha
a64da56134 qcacmn: Stop FISA if frame rings mismatch
If frames from the same FISA flow goes into different REO2SW rings, it
will result in an unexpected FISA behavior. This can happen if the
frames have been reinjected from FW offload module since FW will select
REO2SW1 ring. If the same flow frames hash to other REO2SW rings, then
the same flow UDP frames will do to different rings.
Reo_destination_indication of 6 indicates if the frame has been
reinjected from FW. If so, then continue to deliver the packet without
FISA.

Change-Id: I14a17a10d04909adfb30557d58beb1610e59bf70
CRs-Fixed: 2790292
2020-10-06 23:57:02 -07:00
Adwait Nayak
d4ef2e3959 qcacmn: Fetch cfr info from PHYRX & RXPCU ppdu end tlv
HAL changes to fetch cfr information from
PHYRX_PPDU_END_TLV & RXPCU_PPDU_END TLV

Change-Id: I5817fdc5d17ebea3f2376b7bef9e58981198d1ec
CRs-Fixed: 2752943
2020-08-18 14:43:32 -07:00
Mainak Sen
33d438516f qcacmn: Update hal api for IPQ5018 SG support
HAL spi addition for SG support on IPQ5018

Change-Id: I76179f41cbbf80504ee2e88156783a86bd07e8fe
2020-07-23 04:46:13 -07:00
Neha Bisht
e3876720a2 qcacmn: Add ini config to remap reo destination rings used by host
Adding support for enabling ini config to remap reo destination rings
for HK v1, HK v2, maple and pine platforms.

Change-Id: Id9d304521f32497e3acd845ddd2973b96b641516
2020-07-01 05:42:51 -07:00
Sridhar Selvaraj
3ae6b5c3fe qcacmn: Update REO Remap config API as platform specific
Update REO Remap config API as platform specific

Change-Id: I6a38b87e9181e8bc939e49e3eb55fcd6cace626d
2020-06-12 19:29:39 -07:00
Basamma Yakkanahalli
e2b87fc102 qcacmn: qca5018 changes in rx flow identification
Rx flow indentification changes to provide
support on qca5018 target

Change-Id: Ia2f67ff2b6c6bd1575a48634cf06ffe47ffaebd7
2020-06-11 11:10:01 -07:00
syed touqeer pasha
c6d4cbfd1a qcacmn: qcn9000 changes in rx flow identification
Rx flow indentification changes to provide
support on Qcn9000 target

Change-Id: I1b7ef8c93e38e753cb7014dca68148a4174daa82
2020-06-10 18:13:46 -07:00
Basamma Yakkanahalli
c0b1d0ebf0 qcacmn: use distinct I/O remap to access CE register for ipq5018
In ipq5018 CE registers(0x08400000)  kept outside WCSS(0x0C000000) block.
As both regions are more than 60MB apart, not feasible to allocate
single resource which include both.
So, using a separate I/O region to access CE registers.

Change-Id: I67bb6d5ac82a1c0ed1d3e13f7776f9d69ee19956
2020-05-18 22:33:42 -07:00
Basamma Yakkanahalli
a3f17ee459 qcacmn: Update new chip specific APIs to ipq5018
Added below chip specific changes for ipq5018
1. Read ppdu_id from reo_entrance ring
2. API to extract msdu end pkt tlv information at once
    and store in local structure

Change-Id: Ic23bbd03db0e4ac56d40618378dc4d428f88d083
2020-04-29 06:29:37 -07:00
Radha Krishna Simha Jiguru
8ca2521ac8 qcacmn: Get Rx TLV offsets from structure
Size of the TLVs have changed across generation of chipsets
Offset values need to be configured into DMA register for preheader DMA
Added APIs to get offsets of each TLV based on chip type

Change-Id: Ic011332cbf3a1017f324f246e47c9e2c91441c70
2020-04-22 14:03:08 -07:00
Jinwei Chen
b3e587db52 qcacmn: Support RX 2K jump/OOR frame handling from REO2TCL ring
Support RX 2K jump/OOR frame handling from REO2TCL ring.
(a) configure REO error destination ring register to route 2K jump
/OOR frame to REO2TCL ring.
(b) for 2K jump RX frame, only accept ARP frame and drop others,
meanwhile, send delba action frame to remote peer once receive first
2K jump data.
(c) for OOR RX frame, accept ARP/EAPOL/DHCP/IPV6_DHCP frame, otherwise
drop it.

Change-Id: I7cb33279a8ba543686da4eba547e40f86813e057
CRs-Fixed: 2631949
2020-03-24 19:58:16 -07:00
Ankit Kumar
2bf9b7a18a qcacmn: Initialize command/credit ring for qca8074 & qcn9000
Initialize command/credit ring for qca8074 & qcn9000.

Change-Id: I28087dd4d8f4afddd954c764c2e85da43eaf78f1
CRs-fixed: 2562649
2020-03-01 05:25:24 -08:00
Basamma Yakkanahalli
f9529fbba8 qcacmn: Adding hal support for ipq5018
Added new qca5018 hal folder to add ipq5018 specific changes.
This includes interface files to access ipq5018 hal registers.

Change-Id: I7e19dc7c8719fa175695b268dc904fb4521a3330
2020-02-10 21:56:37 -08:00