In WBM error processing read peer_id from peer_meta_data
instead of sw_peer_id.
This changes is needed because we need to process Rx packet
on ML peer. But in MLO case sw_peer_id field contains
link_peer_id where as peer_meta_data has ml_peer_id.
Change-Id: I3f469adfdf7efa88cb081e94fa9fe0c54c1fb078
In order to support flow overide feature,
AST table has to be split between RxPCU and DDR.
With this split, RX monitor cannot make use of
ast_index to fetch peer as it is not from DDR.
So make use of sw_peer_id to fetch peer.
This sw_peer_id is derived from RX_MPDU_STAT_START_TLV
Change-Id: Ib2a003a2640fded3287c318d2ad59fd3127af9b6
CRs-fixed: 3004363
HAL generic APIs which use HW definitons that
do not have same value across all lithium chipset
are moved to header files. So that these will be
compiled with appropriate header files
Change-Id: I6c167afa4212c5e884f5e18ff1ccb3bbbba8f5f5
Currently the hardware srng register offset is statically
assigned to the handle. This can lead to incorrect index access
when targets (eg: wcn7850) is added which require additional
register offsets to be stored in the hw srng register offset table.
Move to the index based assignment of the srng register offset.
Change-Id: I8e38bdd0c28068029a0267fce706edf4378b9df8
CRs-Fixed: 2965081
Assign th HAL TX/RX ops in a function instead of assining a structure
directly. This can be later extended to have default ops for a family of
chips and then override that with chip specific ops.
This also helps the case where a new hal_soc->ops needs to be added.
The new 'op' will need to be added to only a default ops initializer
(with assumption that it applies to all chips).
Change-Id: Iefa23d14110fa5252444fad89737a3b2b2fbab6f
CRs-Fixed: 2891049
Currently the FW configures the mac with appropriate
offsets for rx pkt tlvs using the structure defined in
te FW and the host does not send the ring selction config
HTT message. This can create a problem when FW stops subscribing
to tlvs or changes its rx pkt tlvs offset.
Fix this by configuring the rx pkt tlv offsets via HTT
ring selection config message.
Change-Id: I1a2865f91b34dd7bda1af8651d7831097dac0bee
CRs-Fixed: 2860504
Change hal_hw_txrx_ops struct to designated initializer syntax for
structs for 5018.
Change-Id: Ie04dc1ebaa4e4964a565416c900c55e309638261
CRs-Fixed: 2837917
Change the alternate indication_0 to WBM instead of
REO2TCL. This is done such that, WBM takes care of
the of the de-linking of the link descriptors and
release the buffers to the respective WBM rings.
WBM should take care of the NULL entries if present
in link descriptor as WBM internal errors.
Change-Id: Ie084e54861bb4611a45cd724bb32d211c62f4f21
In IPQ501x/QCN9100, the REO fragement destination ring
has moved from the REO GENERAL register to REO MISCELLANEOUS
register. Changes are added int HAL_REO_R0_CONFIG to set
the fragmentaion destination value for IPQ501x/QCN9100.
Change-Id: I868dd0ac5c24217f9778ab9da5c2a3d98d3ea302
If frames from the same FISA flow goes into different REO2SW rings, it
will result in an unexpected FISA behavior. This can happen if the
frames have been reinjected from FW offload module since FW will select
REO2SW1 ring. If the same flow frames hash to other REO2SW rings, then
the same flow UDP frames will do to different rings.
Reo_destination_indication of 6 indicates if the frame has been
reinjected from FW. If so, then continue to deliver the packet without
FISA.
Change-Id: I14a17a10d04909adfb30557d58beb1610e59bf70
CRs-Fixed: 2790292
HAL changes to fetch cfr information from
PHYRX_PPDU_END_TLV & RXPCU_PPDU_END TLV
Change-Id: I5817fdc5d17ebea3f2376b7bef9e58981198d1ec
CRs-Fixed: 2752943
Adding support for enabling ini config to remap reo destination rings
for HK v1, HK v2, maple and pine platforms.
Change-Id: Id9d304521f32497e3acd845ddd2973b96b641516
In ipq5018 CE registers(0x08400000) kept outside WCSS(0x0C000000) block.
As both regions are more than 60MB apart, not feasible to allocate
single resource which include both.
So, using a separate I/O region to access CE registers.
Change-Id: I67bb6d5ac82a1c0ed1d3e13f7776f9d69ee19956
Added below chip specific changes for ipq5018
1. Read ppdu_id from reo_entrance ring
2. API to extract msdu end pkt tlv information at once
and store in local structure
Change-Id: Ic23bbd03db0e4ac56d40618378dc4d428f88d083
Size of the TLVs have changed across generation of chipsets
Offset values need to be configured into DMA register for preheader DMA
Added APIs to get offsets of each TLV based on chip type
Change-Id: Ic011332cbf3a1017f324f246e47c9e2c91441c70
Support RX 2K jump/OOR frame handling from REO2TCL ring.
(a) configure REO error destination ring register to route 2K jump
/OOR frame to REO2TCL ring.
(b) for 2K jump RX frame, only accept ARP frame and drop others,
meanwhile, send delba action frame to remote peer once receive first
2K jump data.
(c) for OOR RX frame, accept ARP/EAPOL/DHCP/IPV6_DHCP frame, otherwise
drop it.
Change-Id: I7cb33279a8ba543686da4eba547e40f86813e057
CRs-Fixed: 2631949
Added new qca5018 hal folder to add ipq5018 specific changes.
This includes interface files to access ipq5018 hal registers.
Change-Id: I7e19dc7c8719fa175695b268dc904fb4521a3330
