Stage property is modified for dimlayer during atomic
set property phase. This avoids any commit failure occurred due
to dimlayer checks during atomic check phase.
Change-Id: I4ff3d83a5aa9d6446fd4955f6c29854acf93bc68
Signed-off-by: Prashant Singh <prasin@codeaurora.org>
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
Add support to expose base layer staging property to HAL.
In those targets where base layer staging is enabled in mixer,
layer with zorder 0 will be staged as base layer.
Change-Id: Id825357c61ac6913bdcb8a184fc501236519d5dd
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
Add support to stage layer with zorder 0 as base
layer and stage borderfill only during null commit.
Change-Id: I54356c1b7834227cc3da00c211e71ac5816ce51a
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
wr_ptr_wait_success is true only if wr_ptr interrupt arrives, so
initialize it after display kickoff.
Change-Id: I5790d9dac25352898ece160f6b258b50ca2edefa
Signed-off-by: Ray Zhang <rayz@codeaurora.org>
Update triggered power event to last event correctly,
regardless of whether a callback is called.
Add event log to see debugfs clock rate change.
Change-Id: Ifa9c1ffb450f50a3928eb44362723b6d495b2354
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
RM allocated reservations for the ongoing commit are cleared when
there is a delay in ongoing commit scheduling and back to back
prepare comes. This clearing occurs in the subsequent checkonly
commit with modechange property set.
Timeline of the issue:
--> C1 commit check_only + modeset, RM allocated resources
--> C2 commit check_only scheduled before C1 commit with
check_only + modeset, overridden C1 reservations with
its own into rsvp_nxt
--> C1 commit scheduled and RM committed reservations
allocated by C2.
Change-Id: I46cc924fd6515590e32c8e97a82847d2bde97270
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
CWB connector is tied to primary crtc along with primary connector.
Avoid using CWB connector power state in determining active crtc,
as it is already done via primary connector.
Change-Id: I35ec95349790990c49b9a63afd6e0f55d23b4887
Signed-off-by: Kalyan Thota <kalyant@codeaurora.org>
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
Hardware structures for writeback ctl and cdm are set
to null during wb disable, to prevent crtc mode change
on primary during subsequent wfd and cwb sessions.
Change-Id: I7536203761c615c37c8633d1621951475895400a
Signed-off-by: Prashant Singh <prasin@codeaurora.org>
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
The vsync callback for concurrent writeback is
not necessary. This would conflict with vblank
notification of primary as both belongs to the
same crtc.
Change-Id: Idb67915de086f94feb231d61b6f7e4e068a1ac35
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
During validate, kernel should check if input buffer frame
buffer for wb conn is in secure context. If so, the output
buffer must also be secure context, or fail validate before commit.
Change-Id: I38e50f8b2ac71c8532d9d44df08850bf33180c41
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
Clock rate can be set from debugfs, and this can attempt to
set clock rate even when display power is not enabled.
Set clock rate should check the last power event first.
Change-Id: Ibf01753a288e5a3003928664c99aa6dbf26350d6
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
In dual display continuous splash case, there are certain
scenarios where pipe being used in secondary display at boot up
is allocated by primary crtc. Add check to return failure
in such cases.
Change-Id: I9047b6e7f91e59a9daff5089abb41017c068b449
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
Add null check for pingpong block used during
the commit phase.
Change-Id: I3ebbcfe9c42ee6d1201a141f553bbb0a0ae97ad6
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
For CTL_ACTIVE targets, slave ctl need not to be reserved
as both the interfaces can be driven with single ctl.
Add a necessary check before enabling the feature.
Change-Id: Id68d7dd4fc1cf9534466fd5bfa50c3f551d06ce4
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
There can be few cases of ESD where CTL_START is cleared but
wr_ptr interrupt does not come. Signaling retire fence in these
cases to avoid freeze and dangling pending_retire_fence_cnt.
Change-Id: I167f69dce5cbe43b4771e5056d8a73bd7587e76e
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
Reset MDP ctl path and DSI ctl on autorefresh
disable failure. This will enable the hardware
to recover from the hang.
Change-Id: Ia9acc8573c22e0713179ef4f6ef604caacabfadb
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
This change updates mandatory wb property to
optional as few low tier targets do not have wb
hardware block.
Change-Id: I39e6bf80a527dff95905e0a204401185e9e7bc03
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
BW_INDICATION indication must be programed before BWI_THRESHOLD.
Otherwise, it will revert to legacy behaviour and rsc wakeup is
delayed by one vsync causing janks. In current code BW_INDICATION
is done after LM/SSPP programming and plane fence wait. Moved the
perf_crtc_update before this and just after ctl prepare configuration
to avoid chances of BW_INDICATION crossing BWI_THRESHOLD time.
Change-Id: Ie976720910c34aaf140f1ce7daef38ba20bc10f5
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
Update the DSC initial line calculations to use logical
or operator instead of bitwise operator. Additionally
this change takes care of removing unnecessary brackets.
Change-Id: Ie7fd099e726f0dbed012d5406860300a48d9b2eb
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
This change renames the splash region memory node name
to align the node with the advanced bootloader naming
convention.
Change-Id: Idfd666b5e32e5f22ccb677f68155621adfe87a14
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Separate the horizontal and vertical max downscale checks
as pre-downscale introduced different limits on different
axes. Also cleanup the variable names for max downscale
limit when pre-downscale is not enabled.
Change-Id: If01aac1844d0bd5133502a50dbc38197e11da5d5
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Reduce the cyclomatic complexity for this function by splitting
the work in to helpers and using the new sde_dt_props method of
device node parsing.
Change-Id: Id4a41225bd78f06ee353a636d17330ba41daf1ff
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
This change moves the msm_driver power resource initialization from
bind time to probe time. This keeps the resource vote on until all the
devices are bound. This is required since the regulator and clock
sync_state driver will remove the proxy votes as soon as msm_driver
has probed.
Change-Id: Icb0e59e4ff0290ef0c1bd3914d6fdbf99bf5d9fa
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
This change adds support for programming SPR hw block as per the
client configuration from the respective color property blob.
Currently only reg dma accelerated path is provided.
Change-Id: Ib8559ec2c392be7b69ca43c6364e701fab877a28
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
Currently driver clients are not setting the last value of the igc
table. As a temporary change setting it to 4095, once user-space changes
are updated will revert the current fix.
Change-Id: Ifd6e62cd9edf3d1f2917079f639e00aa4ea31cf1
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
Asynchronous command transfer wait during pre kickoff
is only applicable for DSI. The change ensures that
the flag is set only for DSI connector, otherwise it can
result in memory scribbling for other connectors.
Change-Id: I623f15cf13fcd3ae72f584d5ef8883570a848c93
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Previous SB DMA logic was not clearing a "SB DMA active" flag, resulting
in SB DMA incorrectly being flushed every frame. While this logic
matches the DB DMA approach, it is unnecessary and could result in
delayed DB DMA execution.
Update SB DMA logic to clear the "active" flag for the target DSPP
immediately after the SB DMA is flushed.
Change-Id: I3dc0792a50d7dec42cb32bf8cd1e3d0b217cf582
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
Gamut registers have been updated in newer version of dpu where the
bit depth of the registers have been updated. Change programs
the values by adjusting for bit depth changes.
Change-Id: Id8d8dc37aff6854d67855b9aa7644d1ca4ec4e6f
Signed-off-by: Lakshmi Narayana Kalavala <lkalaval@codeaurora.org>
DSI controller and clock will be disabled/enabled during panel mode
switch, so disallow backlight update during panel mode switch to
avoiding DSI exception.
Change-Id: I37e2f3c9aa929555593ffb53950521150ee7698f
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Avoid esd check during pm_suspend state because core
clock enable will fail. This change adds additional
check and also adds the clock enable failure check.
Change-Id: Ie8bfa4f74d323ff15a07fb037675f07ab942f016
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
This change installs blob property on each crtc for client to program
SPR block configuration based on display panel SPR pattern. Property
installation is conditional only if MDSS hw has SPR block entries.
Change-Id: Ie85423d83b7badc547e75e6eb07ee6b9945f8834
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
This change parses SPR hw block entries from device tree and populate
SPR block as sub block of DSPP block. Change also enables register dump
by registering sub blocks with sde driver register dump routine.
Change-Id: Ic603cd3cc001dddce5dfea61341c166a5fec1682
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
Add a compile time flag for the MST feature that will allow
selectively enabling the feature.
Change-Id: I8bf288277c7af00c3cf254a8c757151559e0a010
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
