This change updates the include file path for necessary dp
and dsc headers that have moved in upstream kernel.
File path changed in upstream:
include/drm/display/drm_dp_aux_bus.h
include/drm/display/drm_dp_dual_mode_helper.h
include/drm/display/drm_dp.h
include/drm/display/drm_dp_helper.h
include/drm/display/drm_dp_mst_helper.h
include/drm/display/drm_dsc.h
include/drm/display/drm_dsc_helper.h
include/drm/display/drm_hdcp.h
include/drm/display/drm_hdcp_helper.h
include/drm/display/drm_hdmi_helper.h
include/drm/display/drm_scdc.h
include/drm/display/drm_scdc_helper.h
Change-Id: Icb9a227c7464061f68fe60cbda6d93858fa768c5
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
LTM block should be disabled when encoder is being disabled to avoid
display hang when all driver clients have been closed.
Change disables LTM hardware block when encoder is disabled.
Change-Id: I279296b566ab93c302e6166b6fa4b7197c2cc0ab
Signed-off-by: Gopikrishnaiah Anandan <quic_agopik@quicinc.com>
In the current code if there is a switch from DSC to non-DSC
mode, all the DSC blocks attached to the sde_encoder are not
cleaned up properly. Due to this, during virt disable these
DSC blocks are disabled and flushed resulting in underruns
on other ctl paths which might be using them. This change
properly cleans up all the dsc/vdc attached to the sde
encoder to avoid such issues.
Change-Id: Ie644701cbda6b4d056bc7ef30300be96096c5214
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
Currently the aux switch is disabled at the end of the disconnect
path which would include the wait time upto 5 secs becauase of usermode
cleanup. However, the PMIC module is expecting the aux switch to be
disabled within 400 msec after the disconnect is notified. If not, this
would trigger an LPD failure. This change moves aux switch disable
further up in the disconnect path, before waiting on completion of
usermode cleanup.
Change-Id: I42e0608f06127729a78de11631d16d0a3ca0d2b4
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Move frame data stats collection/notification during frame-done and
retire fence sysfs notification to event thread. This will free up
some interrupt time.
Change-Id: I2648ac4287ce8712e9a059edd408a59753aa6d32
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
After freeing MST sim context memory the pointer isn't set
to NULL leading to unauthorized memory access. Along with
this fix, this change also defers checking sim device ports
pointer at a more appropriate place in the function call.
Change-Id: I20c09edbd454c9d491060815dc73bae34aab6b08
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Fix the max crtc count based on the number of real layer mixers
available. Usermode can use the crtc count to derive the number
of layer mixers. This will be used in usermode to check if a new
DP/IWE/WB session can be supported by the HW, based on the existing
displays at that point. This will avoid atomic_check validation
failures in driver.
Change-Id: I63b033604ac549fc01bccef2a9320e0befab5926
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Add changes to get drm object reference for connector and
remove out fb in dual display recovery case.
Change-Id: I1fd0c4818575b3f532d51ad41285031e8320c5fe
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
When encoder is disabled, demura is disabled since pipes
are disabled internally.
Change marks the features which were active and disabled
by driver as dirty so that it can be applied in the next commit.
Change-Id: I805d17d673a8ff41f9bdb18ba7f2fd185b5ccb5a
Signed-off-by: Gopikrishnaiah Anandan <quic_agopik@quicinc.com>
Expose the number of cdm blocks available through the connector
capabilities. Add CDM to the topology_control table, so usermode
can use the property to reserve the CDM block during modeset.
Additionally, fix a error code return during CDM block reservation
failure in sde resource manager.
Change-Id: Ib42ca4e8614076a8e5df77d8abc77a9e73674390
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
There is little sense in reading interrupt statuses and right after that
going after the array of statuses to dispatch them. Merge both loops
into single function doing read and dispatch.
Change-Id: I1259476549bcaf9f9f4e12591a7e182796e150dd
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Git-commit: 0abdba47dc1df708c365421d481734d3f7fecb01
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Currently when disconnecting a secondary monitor, RSC will
transition to solver mode. If the bandwidth remains the same
for primary display, SW will not update BW indication register
causing stale TCS wait values.
This change forces a register update when RSC mode is
changed to solver mode.
Change-Id: I99d2332621bad75a7b6abdb64d6aedd35c30ca63
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
This change adds robustness to hpd notification by resending
it if there was no action in 2 seconds, just in case, the
first notification didn't make it to the usermode.
Change-Id: Iaf00669ec77e8c50618ee5618735a98518ad7f1a
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
With real DP over Type-C sinks, DP driver requests access to USB
combo PHY from USB driver. But in DP SIM mode, there is no real
sink and PD management, so the combo PHY is managed by USB driver
and DP driver uses it without actually claiming it. If the USB
cable is unplugged in this scenario, USB driver notifies the
disconnection through an atomic notifier call. It does not expect
the handler to go into sleep, but the disconnect handler inside
DP driver has multiple wait for events and also sleeps to wait for
HW state updates.
This change passes a skip_wait flag to all the disable functions
to complete disconnect processing by skipping all processor sleeps
and event waits.
Change-Id: Ia98de0e7fa6b0573e644615ee59015914a93f4cf
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
DP sim ports created during DP sim enable aren't cleared
during disable path. This would retain the last status of
the DP sim port or the connector. This would impact the
next iteration of DP sim test, if done without device
reset. This change will set the port number to 0 during
DP sim disable and clear the memory allocated for these
ports.
Change-Id: I386a62e87fcaf006db8dd18e5751b33bbe70fc9b
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
This reverts commit 14e7e9b409346aa77fd08cca6eab85252d9ccabe.
Reverting this for now until we properly understand the reason
for command transfer timeouts that we are hitting for 5k panel.
Change-Id: I0390af66f9ca06abc1ebb81996bb683dea35beac
Signed-off-by: Vara Reddy <quic_varar@quicinc.com>
This change adds a debug node named 'crc' to drm_dp to read
the frame CRC values for DP controller and DP Sink. In order
to facilitate the immediate read of the CRC values when
accessed, it enables the CRC calculation on the controller
and sink automatically when the stream is enabled. In addition
to the frame CRC values it also reads the MISR values from
controller and PHY to validate the data flow from controller
to PHY.
Change-Id: I1acee2dba931e4635caf4a400e336a72c86e88bf
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Use with the new connector state during validation phase for
checking the 3d-merge topology, since this is the state that
needs to be validated.
Change-Id: Ie212f948affa4dc439ef508363bac6713e560006
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
MDSS 9.0.0 supports 10 pipes, so modify the max_planes
accordingly. This is used for the frame_data transfer
between user/kernel and since its a new feature added
there is no backward compatibility that needs to be handled
for this uapi change. Add corresponding bound check during
the usage.
Change-Id: I0853fcc55395855d798f2c1b03cf9bf7b4bd3c96
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
This change skips msm_lastclose, when splash enabled builtin-displays
equals number of actual displays and are stuck in continuous splash.
It fixes the issue seen with change commit 548b17185e95
("disp: msm: send power_on event in dual display composer kill scenario").
Change-Id: I1f5417d8945db621dc20ab0a9cc0146eabae5e22
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
This patch cancels all the delayed_off_works if scheduled and flushes
the display threads for completion during msm_lastclose. The commit
from msm_lastclose client modeset to disable any crtcs if enabled is
always scheduled on primary crtc_commit thread. In the current issue,
delayed_off_work is scheduled on secondary display crtc_commit thread
and primary crtc_commit thread is scheduled to turn off active crtcs
from msm_lastclose leading to null dereference access of sde_enc's
cur_master. This race is avoided by serializing the operations in
msm_lastclose.
Change-Id: I30cc95b925c8134f0064816ebe2cfdb86a49fb36
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Currently, driver is determining the amount of memory to allocate
based on the event log object indexes (first, last). The last index
can change if there is additional logging done during the coredump
phase and potentially cause an out-of-bound memory access during
buffer traversal.
This change restrict the event log object traversal to a maximum
of the output buffer size.
Change-Id: I91e5734362d2d7a796129fce85e27611bab2245f
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Add validation during crtc_atomic_check to have crtc width as
multiple of 4 when dualpipe 3d-mux is enabled and multiple of 8
when quadpipe 3d-mux is enabled. This ensures each layer mixer
is having an even width.
Change-Id: I5dc173c1b0349430a8e12a7b1c9440c7854e7ecd
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Avoid shutting down DSI PHY and lanes before entering into
idle collapse.
Change-Id: I62fb40c2398e544b08b8cb8788ac2dc1143a82ce
Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>
DSI PHY has various resets defined to reset analog, PLL and digital
portions. In current sequence, these resets happen after PLL is locked
which can result in introduction of jitter on PHY lanes.Reordering these
resets to happen before PLL is programmed to have intended clean start
of DSI PHY.
Change-Id: I4eb5c05ea0e6015a5447728b2845b49817411c50
Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>
Change increases cmd dma timeout to 1200 milliseconds from 200 milliseconds.
There are video mode panels which can support one frame per second, if pixel
data transfer is active, then our command transfer timeout should be atleast
1000 msec.
Change-Id: I3e8269febe3ed6e55ac9381a8de35e7d19fa3160
Signed-off-by: Vara Reddy <quic_varar@quicinc.com>
This change converts the ubwc stats roi into a blob property. This
allows for the roi data structure to be passed into kernel.
Change-Id: I4b30dcc16bcbd152428861444ff321add860942f
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
