Adds null check for MST port and connector after payload
allocation. Prevents calling mst helper functions with
a null port or connector on a failed payload allocation.
Change-Id: I8e228bd1498b11b302371c1ad6d805d5f941667e
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
Postpone virtual encoder reset until commit done complete
on all the encoders of the crtc to ensure cwb encoder
resources are held until it's primary encoder commit with
cwb resources disable is picked by HW.
Change-Id: I820317d13c00b44f6edd69acff83dc3b494b6282
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
Passing the same error code received from the input fence error.
Change-Id: I59865e89eb974d1ee9f7c2fe3e13acd66cb82617
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Add support for all the configs symbols under config_options under DDK framework.
Change-Id: Iba2949175afe5f55a2e3107d2afd71e55b862d61
Signed-off-by: Varsha Suresh <quic_varssure@quicinc.com>
This change decrements the specific drm connector's reference count
after it has been used for reading crc frame value. Without this
change, there might be a chance of a connector's reference count
still remaining positive, even if it is not accessed anywhere
further in code.
Change-Id: I9058ca046fa114bc10159045f98c40ac68ade751
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
This change limits reglog feature by default to user debug
builds only and provides debug option to selectively disable
reglog for power and perf profiling if required. This change
is needed as reglog is considerably heavy on commit thread
execution.
Change-Id: Id06a63e10fd0c93ba0af6c6f2d1ae36b70c47f67
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
For MST Simulation use case, whenever the port status is updated on
an individual display, send a hotplug event to usermode to make
sure it is handled.
Change-Id: I959290f2c67378e057933356f3ffe692f8b858d7
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Coherency check is done for all kernel revisions during
begin_cpu_access, but the check is limited to older kernel
revisions during end_cpu_access. Fix it to have the
coherency check for all begin & end cpu access.
Change-Id: I03ada0d7dea6875f0be7b4f807738480bcfb3c70
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
Replace DSI_CTRL_ERROR with pr_err_ratelimited to reduce PHY contention
logging errors, as excessive logging in kernel can lead to system crash.
Change-Id: Ibd81a0e852a73186144ebefc8a1c09020a6e74f0
Signed-off-by: Rohith Iyer <quic_rohiiyer@quicinc.com>
update error handling to not error out when demura is disabled.
Change-Id: I06a7ccc3008e8d96ac8883551e5f6a7894b6653d
Signed-off-by: Sanskar Omar <quic_sansomar@quicinc.com>
Enable DP AUX IPC logs for GKI builds to allow more complete
log collection.
Change-Id: I2f61c167d5856f1d310b4c7145cb18dbb5d7d6dd
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
This change adds detect_ctrl to tear_check block and
programs it to its default configuration.
Change-Id: I7665b373a6cd846bf5979c2dc02bc0bdfdf309ab
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
This change avoids wait for EPT to timeout in non-qsync panels
when the EPT time is within last & next expected vsync time
calculated based on current fps for panel.
Change-Id: I9e385c14a20994b29b5bc4afb024f147e6cc035c
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
During drm_bridge_mode_fixup, we deny a simultaneous crtc state
change and seamless variable refresh. Incorrect translation logic
between drm_mode and dsi_mode made it such that whenever the dsi
bit clock is not the default value, any drm commit would be marked
with the variable refresh flag, denying all suspends. This change
fixes the suspending issue.
Change-Id: If3c1f603af3e2917f82be6487bee1084a6e1b605
Signed-off-by: Kirill Shpin <quic_kshpin@quicinc.com>
Extension bits of test point selection is needed when test
point value exceeds three bits, not based on blcok id value.
This change fixes debug bus test point selection when
value is more than 3 bits and extension bits are required.
Change-Id: I37688b2c6e476b1271daad0bbddb5896edc530d1
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
Set the number of layer mixer for each wb mode based on the
current mode hdisplay width. If the hdisplay width of current
mode is greater than the maximum layer mixer width of HW supported,
set dual layer mixers for this mode and check if the split
hdisplay width is an even number.
Change-Id: I0190830ed559f008f9e2c0752858ddc5e7cb83cd
Signed-off-by: Lei Chen <quic_chenlei@quicinc.com>
In userspace, the backlight scale of LTM will be set to the maximum value
in the suspend case. However, sometimes this value is sent to the driver
after resume. This will cause a backlight flicker issue.
For fix this issue, this change resets the backlight scale in the suspend case.
Change-Id: I0eb586eeefbf3444d6f44281d58789460300dffc
Signed-off-by: Yuchao Ma <quic_yuchaom@quicinc.com>
The driver currently inserts a failsafe mode when EDID read fails
for SST. But for cases where the edid read succeeds but all the
modes are getting filtered out because of resource availability,
the driver does not add the failsafe mode. But the usermode
expects the failsafe mode to be always present in the mode list
as per DP specification. Also, the driver currently does not
add the failsafe mode, if the edid read fails on an MST monitor.
This change covers all these missing cases and makes sure the
failsafe mode is always in the connector's mode list if it is
in connected state.
Change-Id: I92eeaa00ad7b26a18b3689aa1c2ada4244aba3bc
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Allocate DSC inversely for non built-in displays to avoid Quad DSC
can't be contiguous reserved as the below scenario.
Use case: Primary display with 2 DSC, and DP display can support 8K@60
with 4 DSC and 4k@60 with 2 DSC.
--> when both display are in powered off, all DSC blocks are free.
--> enable DP display with 4k@60.
DSC 0/1 is allocated by DP display
--> enable primary display.
DSC 2/3 is allocated by primary display.
--> switch DP display to 8K@60
DSC 0/1 + DSC 4/5 are allocated by DP display.
But the DSC must be contiguous allocated for Quad pipe.
Change-Id: I465c115bb7ec775483dc6a984306a9aa51750b14
Signed-off-by: Lei Chen <quic_chenlei@quicinc.com>
