This change clears all link info capabilities as a part of
panel deinitialisation during a disconnect sequence. Without
this change, the link info capabilities like the CRC flag will be
retained for the next hotplugged device. Now if, a MST is connected
after a SST connection, the base panel will have the CRC value of the
previous sink, which will be invalid for the case when the hub doesn't
support CRC.
Change-Id: I3a820070fd5006a707328b4d192893a465c04448
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
To optimize evt log entries, spinlock is been removed and
used atomic operator for curr variable, due to which there
is mismatch of count values between curr and last variable during
xlog dump in kernel. So change the last variable to atomic to
avoid race condition between entries of evt logs.
Change-Id: Idf3e2b982261d77fec97985af1e8bf740a6f6197
Signed-off-by: Ryan McCann <quic_rmccann@quicinc.com>
Update the string formatting of debugbus dump header
to support existing scripts for debugbus parsing.
Change-Id: Ie0b4fdcb73e131ea5893a3dbc6aad969735d137d
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
During HPD High, the driver sets the CONNECTED state and then performs
a sequence of initialization operations. If any of them fails, it should
properly unwind the executed operations to restore the driver to its
initial state. This change adds error handling paths in the hpd high
handler to do just that.
Change-Id: I66a77ff73b7c11d0a59d80b8df3c4ea49a4ed3a6
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
During qsync frequency step down, it is possible for the changing
frame window to lead to frame buffers being transferred when it
is unsafe to update. Pineapple r2 hardware supports using the
panel's TE level, instead of the start window, to trigger the
frame transfer.
This change enables using TE level during QSYNC or AVR, if the
hardware supports it.
Change-Id: Ie675edaaeb80921c639905395b709f4c67134fc7
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Reduce the MDSS IRQ processing latency by skipping the status
register read/write of the interrupts which are not enabled.
Change-Id: Id86057ad3ab043ad76d4d4b44a373eff3b55da4d
Signed-off-by: Shirisha Kollapuram <quic_kshirish@quicinc.com>
Support 8bit and 10bit bpp switch for display.
Change-Id: Ia5fcb330df95618596377773d0598be2b5609de1
Signed-off-by: Yahui Wang <quic_yahuiw@quicinc.com>
During MST display enablement, the time slots for the display are
calculated during mst atomic check, which is then used in the
enable path. But if for some reason the payload wasn't allocated
successfully, then the enable path will have the time slots set to
0 which causes a send video timeout and also the missing payload
could result in null pointer dereferencing in step2 of mst payload
addition.
This change checks for this situation during pre-enable and returns
an error so the enable does not continue ahead.
Change-Id: If139707537b7a6dba169841ac82841851b4c09cb
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Previously we were updating internal layer mixer allocation
bookkeeping during every mode validation regardless of whether
the mixers were already designated in use, resulting in double
counting of in-use layer mixers.
This change prevents modification of these values if the given
connector's mode has already been previously validated so valid
modes can be returned properly.
Change-Id: Iea5dccfbc4087cc76f186101d38b605792326b16
Signed-off-by: Andrew Bartfeld <quic_abartfel@quicinc.com>
Disable CWB in quad pipe for quad LM CWB not supported
to avoid out of bound access.
Change-Id: I7e64cf132489401f91621ccde31cba68c8076d28
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Change increases cmd dma timeout to 1200 milliseconds from 200 milliseconds.
There are video mode panels which can support one frame per second, if pixel
data transfer is active, then our command transfer timeout should be atleast
1000 msec.
Change-Id: I3d650d787fa6557ce474aca977906b99af1f1cbc
Signed-off-by: Rohith Iyer <quic_rohiiyer@quicinc.com>
CPU qos_mask populated from devicetree can have defective cpu cores
included. This change identifies and replaces the defective cores
in the qos mask with the next possible working cpu cores.
Change-Id: Ie6bad11ff36f8e2486ef568b67b3fe024f9786c7
Signed-off-by: Andhavarapu Karthik <quic_kartkart@quicinc.com>
Remove the validation check that rejects the concurrency of
Expected Present Time update during modeswitch, as it is
expected to get an updated EPT value during the switch.
Change-Id: Ia94aedc4ea39b9c72fb0db17e91a09a77086563b
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Move Expected Preset Time delay from prepare_for_kickoff phase to
just before encoder kickoff. This will ensure the delay is done
towards the end of frame trigger and keeps minimal s/w programming
after the delay. This will help in cases where other unexpected
system delays occur, while coming out of sleep.
Change-Id: Ia04a9ab0455db8082b3f9f03d02db2cec5e17db5
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Sets DSI priority level to 7 before any commands are triggered.
This DSI priority setting is recommended by systems team as DSI
and Lutdma uses same Xin for fetch.
Change-Id: Ife6dee5ed51874818168d92728f76108495b8727
Signed-off-by: Rohith Iyer <quic_rohiiyer@quicinc.com>
A dummy LUTDMA region is registered prior to parameter validation, potentially
causing the usage of an unallocated memory if the sde_mdss_cfg structure is
invalid. Update the code flow so that the dummy LUTDMA region is registered after
all parameter validation
Change-Id: I9a10b166ee7a611b9d5d2cb0555822996d123c10
Signed-off-by: Christopher Braga <quic_cbraga@quicinc.com>
When there is runtime PM suspend and a video mode panel is Doze
state or Doze suspend state PM suspend will fail as clocks are on.
To avoid this do a suspend commit while entering runtime PM suspend
so that xo shutdown will be successful.
Change-Id: I108184bf2e5ea18ef54eab879556e9c941514176
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
Add a new clear_flush_mask ops in sde_hw_ctl_ops.
Flush mask update to cancel the fence error frame with
the new ops.
Change-Id: I8d03d8e83a05a652789fb38e885a3c8497e4d262
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Fence error handling for wb and cwb retire fence.
Signal the retire fence for the fence error frame.
Change-Id: I0f73195c50edab4b8aefb58cea342214be87584c
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Reset lut dma when fence error is seen to reset the already
submitted queue.
Change-Id: Iba9ab33a2e80bdaba6b1d4ccff086e3a46f8374d
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Add framework for display submodules like PP, DSI, DP to register
for fence error and call the client callback funtion when fence
error occurs.
Change-Id: I70cc6b01907177e6c4238c4398fe2c085a000322
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Sw fence error handling addresses following:
a. out of order handling
- For cmd panel, signal the release fence and retire fence once
sw fence error detected.
- For vid panel, signal the fence error frame release fence and
retire fence once sw fence error detected, hold the release
fence of last good frame till next good frame.
b. avoid BW decrease vote
c. lut dma reset
d. cancel kickoff
Change-Id: Ic496c532a26d80e0ef0074624ef6ace01c4ab2f0
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Each rectangle is listed as an individual DRM plane, and since
they share a common VBIF register, there is no need to re
program the QOS remapper for the virtual plane.
Change-Id: I7af6aca1953cd61e622ef5b15353d5ea20fd73cd
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
Handle out of order dma fence signalling and propagation of fence
error. Out of order fence signaling is required only in Video mode.
For example, in case of N, N+1, N+2 frames where N, N+2 are good
frames and N+1 is frame with fence error. The release fence signal
sequence in video mode would be N+1, N, N+2.
Change-Id: I8b6f88cfeee945e28571b765f24ffea22fad23b8
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Register callback function to hw fence driver and implement the
callback funtion.
As part of fence error handling, address out of ordering of HW
fences, SW override for release fence signal and handle BW voting
in both cmd and video mode.
Change-Id: I22902762b4cc09a5f5a20cf0dd01fc336a0f0cb4
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Add a new property CRTC_PROP_HANDLE_FENCE_ERROR for userspace
to enable or disable fence error handling.
Change-Id: I72370f405c5299c603b0d673720c28a68c00807a
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
The DP MST driver calculates the PBN value for each mode during
mode enumeration. This PBN value is later used to calculate slot
count and also MST RG parameters. But if DSC and/or FEC is enabled,
then the slot calculation needs the PBN with overhead, but
RG calculator needs the one without. But currently, the driver is
using the PBN with overhead for both. This double counting of the
overhead for RG calculation causes MST FIFO overflow for certain
usecases.
This change fixes this by caching both PBN values during mode
enumeration and using the PBN value without overhead as input
to RG calculation.
Change-Id: Id58e91068c25202e6528a793ab736bc51732961f
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
