Added end point, resource config, GSI configuration and
SRAM entries for IPAv-5.2
Enabling IPA, GSI driver compilation as vendor DLKM
modules for pitti target.
Change-Id: Ib0ae6d6605f11a2b08c63782f8a11d8011d46bbe
Signed-off-by: Pavan Kumar M <quic_rpavan@quicinc.com>
WDI channels do not require userdata. Avoid allocating userdata for new
WDI protocols as otherwise allocations might fail due to large allocation
size resulting in pipe setup failure.
Change-Id: I7630a9c5b450937b264cdeb4b45ace70fd160be3
Signed-off-by: Chaitanya Pratapa <quic_cpratapa@quicinc.com>
When opt dpath is enabled, make changes to stop and start the
channel only when it is required.
Change-Id: I849ccbe969a6c965b18022f3c23e545902d551e2
Signed-off-by: Chaitanya Pratapa <quic_cpratapa@quicinc.com>
Make changes to enable IPA driver for pineapple. Fixed
compilation errors related to kernel upgrade.
Change-Id: Iecbe152fe0b6860616a9a63504d57b92a70ef72e
Signed-off-by: Michael Adisumarta <quic_madisuma@quicinc.com>
Addded change to enable support for hamilton chipset as part of
pinnacles.
Change-Id: Ie8f58c1b385780e778b80f7581c81e2f1a7b6b44
Signed-off-by: Raghavendar rao l <quic_rlomte@quicinc.com>
* update number of channels to collect in reg_save
* enable collection for uC channels
* parse gsi fw version
Change-Id: Iae5bd9e56b076717e7a157b0883b1efb7681c061
Signed-off-by: Dor Deri <quic_dderi@quicinc.com>
The debugfs functions may be called while the GSI is not clocked.
This will lead to kernel panic due to bus error.
Fixing by clock voting before IO access and unvoting after.
Change-Id: I99b1f69df9be5774d688029886b1aef8dfacc657
Signed-off-by: Ilia Lin <quic_ilial@quicinc.com>
Adding support to save ipa/gsi ipc logs in minidump.
Change-Id: Ic83b173140aae5c985a497f7333596c540b094ff
Signed-off-by: Ashok Vuyyuru <quic_avuyyuru@quicinc.com>
Initial version of minidump support in IPA driver.
Change-Id: I73e98fd647dd487dda90049f5b0c5609f558aa92
Signed-off-by: Ashok Vuyyuru <quic_avuyyuru@quicinc.com>
The DMA address allocated may be in 64-bit address
range if dma mask is set to 64-bit, the MSB register
value is required.
Signed-off-by: Cheng Zeng <quic_chenzeng@quicinc.com>
Change-Id: Ie091b01ac44e70d450a8d050855b5f3f0f510695
The pointer should be event ring pointer, not transfer
ring pointer, it has chance to get wrong upper 32 bits
when smmu is disabled.
Signed-off-by: Cheng Zeng <quic_chenzeng@quicinc.com>
Change-Id: I8aa0d102d81fb2632ce988fcc8d816e7fed7b5b1
There are new IPA 5.5 hardware coalescing enhancements that relate to
WAN Coalescing. They are attended to herein.
Change-Id: I54f2655458d90d3b6111a970329b6b56016776f4
Signed-off-by: Michael Adisumarta <quic_madisuma@quicinc.com>
Add changes to register offset. Due to which
GSI channel allocation fails.
Change-Id: Iba36fe8c9124339316788a4396127bc7a9b1485f
Signed-off-by: Praveen Kurapati <pkurapat@codeaurora.org>
Retrieves debugfs data for both ethernet clients in case of Dual NIC mode.
Change-Id: I62eb6af1dedaa738674979520d393c753c0f0190
Acked-by: Eliad Ben Yishay <ebenyish@qti.qualcomm.com>
Signed-off-by: Ilia Lin <quic_ilial@quicinc.com>
Add support for 2 new seperate MSI interrupts
to pin rmnet_ll and rmnet_ctl processing to seperate
CPUs.
Change-Id: I83977081a72d734622525732a97f8563fb530ade
Signed-off-by: Michael Adisumarta <madisuma@codeaurora.org>
Adding debug and register prints for flow control enable or disable.
Change-Id: Id6a79880340cc3e7503da6add3ce9aaf9d0a991d
Signed-off-by: Michael Adisumarta <madisuma@codeaurora.org>
In some cases GP_INT1 interrupt not receiving even GSI FW send the
interrupt. In those cases cases reading the flow control command return
code to check completion.
Change-Id: I329550ab94af9caac870c6050761d3701f0517cd
Signed-off-by: Ashok Vuyyuru <avuyyuru@codeaurora.org>
Changes include null check for IPA netdev and gsihal_ctx.
Change-Id: If897281663e0ae0f29b7110fcbaa4dd98f67eb8d
Signed-off-by: Michael Adisumarta <madisuma@codeaurora.org>
Includes support for IPA stats to be able to send log packet
to ipa_lnx_agent and then to SPEARHEAD framework.
Change-Id: I3112fc6b2e66e15140f638bfff9905bba6997e46
Signed-off-by: Michael Adisumarta <madisuma@codeaurora.org>
With u16 variable not fitting the higher ring size. So
adding changes to chnage ring type to u32.
Change-Id: Ib16e2426071c642f7e25beb022661dfa914cd0c4
Signed-off-by: Ashok Vuyyuru <avuyyuru@codeaurora.org>
Increase timeout while waiting for FC command to complete.
For enable FC command wait longer in case PENDING bit is set.
Change-Id: I6d4443b1688d2ae426079638216829a4ddb30d94
Acked-by: Nadav Levintov <nadavl@qti.qualcomm.com>
Signed-off-by: Sivan Reinstein <sivanr@codeaurora.org>
In some cases for updating the return code in SCRATCH register taking
time after raising the global interrupt. Adding changes to wait for
some time read the SCRATCH register again and also printing the
test bus registers and Q6 channel state in failed scenario.
Change-Id: I4112a2290739daa79629f718d9725258518aba4c
Signed-off-by: Ashok Vuyyuru <avuyyuru@codeaurora.org>
Clear IEOBs as part of CH stop for channels with MSI IRQ type
Change-Id: I7b9af7f385b0876fc2f43314bd3588110911a021
Acked-by: Nadav Levintov <nadav@qti.qualcomm.com>
Signed-off-by: Sivan Reinstein <sivanr@codeaurora.org>
Includes low latency data pipe definition and
support for waipio.
Change-Id: I0158eb15b38de0dfd2b0052b699c69a7c7f58fa1
Signed-off-by: Michael Adisumarta <madisuma@codeaurora.org>
In suspend scenario while checking channel empty scenario
updating the event ring RP pointer from direct register, it
may cause mismatch in reading in polling context. To avoid
discrepancy reading RP pointer DDR location.
Change-Id: Ie198ea9ace033e31463acd974f10dccdcac45c55
Signed-off-by: Ashok Vuyyuru <avuyyuru@codeaurora.org>
Add GSI profiling stats data and the GSI FW version to debug fs.
Change-Id: I5749339f5ec9656e636a512668025bb09a97a3ec
Acked-by: Nadav Levintov <nadavl@qti.qualcomm.com>
Signed-off-by: Sivan Reinstein <sivanr@codeaurora.org>
Add AQC head_ptr_wrb_mod_threshold to gsi event scratch
and configure according to required value.
Change-Id: Ie1234d76b20fe9e17d5a0a295f748a5876ef4ddd
Signed-off-by: Amir Levy <alevy@codeaurora.org>
