Set a flag to avoid multiple reading of sde_dbg info, that
reduces devcoredump reading time.
Change-Id: I83f77dea35bb818d51b0982124a54ffeef7db8af
Signed-off-by: Bruce Hoo <quic_bingchua@quicinc.com>
Enable trusted vm flag for kalama target
Change-Id: I2f2c0a838914d5fccf6642690c082c592e04e38d
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
SID registers and offsets are changed in display
MDSS 9.0.0. Changes are made to program these new registers.
Also, added new revision check for backward
compatibility.
Change-Id: I4e1ea374f38c95a4d1019c2596418bb6bb7c5347
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
Update HFC layer checks to handle partial update. Layer checks
should compare against ROI when partial update is enabled.
Layer checks should compare against full panel height when
destination scaler is enabled. Destination scaler and PU
concurrency is not supported.
Change-Id: I3435370a81f05a492411433054ae09f2125c6bf7
Signed-off-by: Anjaneya Prasad Musunuri <quic_aprasad@quicinc.com>
This change adds the programming of the master interface
register for single interface configurations.
Setting this register is required by hw-fencing feature
to distinguish primary interfaces vs wb.
Change-Id: I84936ebd6a9f2d67cf98c19a51ce3a132c648a2d
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
Because of changes to ref clock frequency, few of the pll
reg values are different for kalama compared to palima.
This change differentiates between these two 4nm versions,
based on pll revision and also introduces a pll reg table
to differentiate the values.
Change-Id: I016330ded10ab334012daa8cc288a8cd5c039f58
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
This change avoids null pointer dereference in different APIs.
Change-Id: I01eba9d64fa4ba2fd81f7f39f586867e22d66771
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
Refactor the function 'dsi_display_get_modes' to
reduce its complexity.
Change-Id: I1a8ecaa780e5070bac7fa40404677c0a8a5d7cd8
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
Mitigate errors to debug logs on non-parsed regulator look ups. Callers
can make use of the return value to handle failures.
Change-Id: Ib0ed869e92104ac7e859484b247ac99bf332fa5c
Signed-off-by: Jeykumar Sankaran <quic_jeykumar@quicinc.com>
MDSS 9.0.0 added support for logging MDP_VSYNC timestamp. Use it for
video-mode panels and rely on PANEL_VSYNC timestamp for cmd-mode panels
as it relies on external panel TE.
Change-Id: I09b25d893075bee7cb2da98d4c4b4e54eb09bd6e
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
With MDSS 9.0.0, s/w relies on the ctl-done-irq which signifies the
frame done for the ctl path. Avoid unnecessary waits during
tx-done/commit-done on the individual physical encoders when ctl-done
feature is enabled.
Change-Id: Ie5e8b08c47a4778dfa03a87dbbae8daf6a738e6a
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Fix the Watchdog timer load value calculation with jitter feature.
Change the long term jitter value check to have jitter < 10.
Change-Id: If834e16d3b8fad5009642e479f529fa5b7cf2d17
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
SPR hardware can be configured by user-space clients in bypass or
normal mode. Change adds support to allow clients to enable spr
in bypass or normal mode.
Change-Id: I04641774de91ec2b40af00c665ceffd72a255eea
Signed-off-by: Gopikrishnaiah Anand <quic_agopik@quicinc.com>
DP PLL driver is the clock provider for link_clk and pixel_clk source
clocks. Once the PLL is configured, the clock rates for these output
clocks must be explicitly set using the clk_set_rate() API so that
the clock framework can correctly compute any MND values required
to satisfy the requested rate at the branch clocks that source from
the PLL output clocks.
Change-Id: I14f8f58333ac5ba3f547d12a123cb5e5f05c6005
Signed-off-by: Aravind Venkateswaran <quic_aravindh@quicinc.com>
Change removes the dependency of reading MVID and NVID settings
from dispcc registers and calculates the values locally in displayport
driver.
Change-Id: I9ad66aea44a3cbc0f739060c49e23d389022a48a
Signed-off-by: Vara Reddy <quic_varar@quicinc.com>
Swing/Pre-emph, SSC, and CLKBUFLR values updated to match
latest changes as per kalama HPG.
Change-Id: Iae96b38f0f8c39280081ae43b41f73ea10f6ddb7
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Signed-off-by: Vara Reddy <quic_varar@quicinc.com>
Enable DP and DP_MST compilation flags for Kailua.
Disable ext audio and HDCP until validated.
Change-Id: I7f05e370aed1df07beff568b87cf12ff57b96d63
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Signed-off-by: Vara Reddy <quic_varar@quicinc.com>
msm_external_display module should be linked as an
additional dependency for display drivers. This change
includes the respective module.
Change-Id: Id16f22f073f596f360d576147e4a0d96c16505e7
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Signed-off-by: Vara Reddy <quic_varar@quicinc.com>
On kailua onwards USB3 DP SSPHY power is control using GDSC.
This change adds support to vote for GDSC when displayport
driver is active.
Change-Id: I2e741f2091018f5dae9a1e7e886179bc6b982d40
Signed-off-by: Vara Reddy <quic_varar@quicinc.com>
Add check to avoid more than 1 CWB active per commit as
hardware doesn't support multiple CWB even if they are
on different OP.
Change-Id: I13416cc2af881de0d8bdd6544a4fdc180fb7a050
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Avoid read/update for WD_TIMER_0_CTL2 register as the default value changed
from MDSS 9.x.x to disable clock granularity and this leads to issues with
VSYNC generation. Instead program the necessary configs directly.
Change-Id: Id545ad772480f94cf432bff8e8bfeb2b679f8aa9
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Ensure SDE_ERROR error log print function name and line number.
Add a macro DISP_DEV_ERR as a wrapper of dev_err to ensure origin dev_err
will print function name and line number.
This would help with analysis of errors reported with automated testing.
Expected display error log format:
[FUNCTION_NAME:line] ERROR_MESSAGE
Change-Id: I354f45b492059d5ba2bb110d56443fd338add7ad
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
If display cont-splash is enabled, then sde irq will be enabled
after registration, but sde power event assumes irq to be disabled
by default and will still try to enable irq with first power event
call, then could cause unbalanced irq enable warning on boot up.
Change-Id: Ic5482dd06501721664994f77cd5764140afb7a62
Signed-off-by: Yahui Wang <quic_yahuiw@quicinc.com>
The sde power event function needs to get actual sde kms irq
number to handle irq update call, but it is not able to know
the irq number before irq installation, so move sde power event
call into kms post init to avoid unbalanced irq issues.
Change-Id: Id262b86f98299fbb9a51c9ccb8e68c7bde7f57ed
Signed-off-by: Yahui Wang <quic_yahuiw@quicinc.com>
This changes takes pitches into account for alignment check
of destination writeback fb. As per HW recommendation
the stride needs to be a multiple of 256 bits.
Change-Id: Ib823a8d309f7ed579d701a4bf56772ce318fb1f5
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Update the RSCC SEQ_MEM_0, SEQ_BR_ADDR register offsets and
the SOLVER_MODE_PARAM1 value for rsc drv version 3.0.0.
As part of the change, remove deprecated is_amc_mode function.
Change-Id: If9e97a9e5ce4a84738d9867cb26dd47cdd6c4a19
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
This change avoids writing of BW_INDICATION registers on each
frame, instead it updates only when there is a change in bandwidth.
Change-Id: Iae32ceb065d2e49e81c2febbbac5508a624d090e
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
The splash memory initialized by the bootloader needs
to be released after the first frame update. Add
memblock_free() call to release this memory that was
reserved during the kernel boot.
Change-Id: I463139a3f930dd9284d3ba9516714ead0c77cc02
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
* quic/display-kernel.lnx.5.10:
disp: msm: sde: avoid error during fal10_veto override enablement
disp: msm: update copyright description
disp: msm: sde: configure dest_scaler op_mode for two independent displays
disp: msm: dp: updated copyright set for 4nm target
Revert "disp: msm: sde: consider max of actual and default prefill lines"
disp: msm: sde: Reset backlight scale when HWC is stopped
disp: msm: dp: avoid duplicate read of link status
disp: msm: dsi: update vreg_ctrl settings for cape
disp: msm: fail commit if drm_gem_obj was found attached to a sec CB
disp: msm: dp: updated register values for 4nm target
disp: msm: sde: update framedata event handling
disp: msm: dsi: Add new phy comaptible string for cape
disp: msm: sde: software override for fal10 in cwb enable
disp: msm: update cleanup during bind failure in msm_drm_component_init
disp: msm: sde: dump user input_fence info on spec fence timeout
disp: msm: sde: add null pointer check for encoder current master
disp: msm: dsi: enable DMA start window scheduling for broadcast commands
disp: msm: sde: avoid alignment checks for linear formats
disp: msm: reset thread priority work on every new run
disp: msm: sde: send power on event for cont. splash
disp: msm: sde: always set CTL_x_UIDLE_ACTIVE register to "1"
disp: msm: use vzalloc for large allocations
disp: msm: sde: Add support to limit DSC size to 10k
disp: msm: sde: add tx wait during DMS for sim panel
disp: msm: dsi: add check for any queued DSI CMDs before clock force update
disp: msm: sde: correct pp block allocation during dcwb dither programming
disp: msm: sde: avoid setting of max vblank count
disp: msm: sde: add cached lut flag in sde plane
disp: msm: sde: avoid use after free in msm_lastclose
disp: msm: sde: update TEAR_SYNC_WRCOUNT register before vsync counter
disp: msm: dsi: Support uncompressed rgb101010 format
disp: msm: sde: update idle_pc_enabled flag for all encoders
disp: msm: sde: flush esd work before disabling the encoder
disp: msm: sde: allow qsync update along with modeset
disp: msm: dp: avoid dp sw reset on disconnect path
disp: msm: sde: consider max of actual and default prefill lines
disp: msm: ensure vbif debugbus not in use is disabled
disp: msm: sde: update cached encoder mask if required
disp: msm: sde: while timing engine enabling poll for active region
disp: msm: enable cache flag for dumb buffer
disp: msm: sde: disable ot limit for cwb
disp: msm: sde: avoid race condition at vm release
disp: msm: dsi: set qsync min fps list length to zero
disp: msm: sde: reset mixers in crtc when ctl datapath switches
disp: msm: sde: update vm state atomic check for non-primary usecases
disp: msm: sde: reset CTL_UIDLE_ACTIVE register only if uidle is disabled
Change-Id: If480e7f33743eb4788549f853ba05e744ecb38d3
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
