Update the prealloc size for RXDMA_BUF and REO_DST
rings using the ini values which have been configured.
Change-Id: Id47fbca3a79b37bba902d1b5bd0bf8c6073648cc
CRs-Fixed: 3283986
add debug prints and a custom timer for how long to wait to receive next
bk pressure event message.
Change-Id: I5a736b0f134cd179990de536da02967db3e39774
CRs-Fixed: 3273427
Add framework to use different RX hash values and ring masks
for ML and non-ML peers
Change-Id: I098cb50b8873eb137ce096011d01a5c21aaf854f
CRs-Fixed: 3269916
At 802.11BE 320 MHz throughputs, flow collision and
the resultant flow eviction can lead to throughput
degradation. Skid length is a parameter which can be
used to reduce these continuous flow eviction from the
FISA flow table.
Increase the FISA flow table skid length to 16 to reduce
the chances of flow eviction from FISA flow table.
Change-Id: I3badcb364d45b19a8a266fe335df320c30f999ae
CRs-Fixed: 3232508
With KIWI_V2, wbm_ring_num for WBM2SW5 and WBM2SW6 have been changed
to 5 and 6. Hence properly update them in g_tcl_wbm_map_array. At the
same time, tx_ring_mask_msi and tx_ring_near_full_irq_mask are also
updated.
With IPA_OFFLOAD enabled soc->tcl_data_ring[0|1|2] is used by HOST
and the other two rings are allocated to IPA usage.
Change-Id: I4c13d0787e46be667c3a5a0ae624df8c2b2b354e
CRs-Fixed: 3229375
UMAC HW reset feature will be using the last interrupt context in each
DP interrupt combination i.e., on a system with more than 8 MSIs for DP,
UMAC HW reset will be assigned a dedicated interrupt context.
Add the necessary support for the same.
CRs-Fixed: 3163900
Change-Id: I26abd01e4261661ed95e1aa3cb2a774e78b50d9f
Enable bits in WMI_INIT command to let the FW know about host's
capability to support notify frame feature. If the feature is enabled,
host can mark certain TX frames as "notify frames" for hardware and they
need not be sent to FW. FW depends on this capability exchange to decide
whether to install HW rules for frames to be sent to HW.
Change-Id: I7158e79ae0fbdc73a2f4096ae1577337e8291246
CRs-Fixed: 3209399
NAPI scale factor should be configured based on the board
type. for example Hawkeye could have a different scale factor
compared to Alder.
CRs-Fixed: 3212330
Change-Id: Ie0bad6aade9ca9379997aa974154f9fb903ab93e
Add ini support to configure TC ingress filter priority
value which would be used for TC based dynamic GRO.
Change-Id: I1742f4539353939e3a40ff4096b3f833f2029b12
CRs-Fixed: 3206817
Currently, data stall detection is without control over
individual data stall events.
INI variable, gEnableDataStallDetection is converted from
boolean to unsigned int which provides control over events
across FW and host with each bit corresponding to different
data stall events.
Bit 0: Enable all data stall events if set.
Bit 1-30: mapped to data stall events. Used when Bit 0 is 0
Bit 31: Enable aggressive timeout for WLM Mode.
Change-Id: I4656520accd1589e77d5054eaa0a3cb8e63b14b2
CRs-Fixed: 3174906
Enable the 4th Tx. completion ring to save CPU load
Initialization and interrupt handling for 4th completion ring
is done here.
Change-Id: I2db27218a3c3e14d719d012f03454a6a7aa647fe
User can specify a limit and frames are dropped when the memory
used by packets in the queues goes beyond the limit. This is a
SoC level param.
Change-Id: Id2bd9caaa11d9ea9f9e04c635ff629190bb62916
Add the PPE Tx HAL data structures. Also add
dummy functions for reo2ppe and ppe2tcl rings
intializations.
Change-Id: I31fa61a728535c32ea3678407da8ae39f0d9f48d
For WCN7850, the first mac (i.e.. MAC0) is capable of
2G/5G and 6G data transfer. Hence initialize and use
only on RXDMA monitor status ring.
Change-Id: Idb6e23a887a9ed32a52dd54765e5ed3c6a12df06
CRs-Fixed: 3094138
WCN7850 has only one RXDMA DST ring, as opposed to other
lithium family chipsets, which had 2 RXDMA DST ring.
Refactor the code to pick the number of rxdma destination
rings from CFG context.
Change-Id: I20d475c02690043e969bc7a78605809b8c6814ae
CRs-Fixed: 3084440
Use chip ID and destination peer to determine the target soc
and partner vdev for Intra-BSS in MLO case.
Change-Id: I709c52e74426c5e81b50c8063cad7669c0e7002d
Offsets used by host for HTT stats are not aligned as per the
structure declaration given in file htt.h .
Make change to use the correct offsets to get the correct stats.
Also make change for byte count computation.
Also make cleanup changes for FR65817.
Change-Id: I8bc6164cc4994c49536d7277779f25b258be1592
CRs-Fixed: 3082742
Add configuration at SOC level for hw vdev stats in BE architecture.
Following config parameters are added:
vdev_stats_hw_offload: option to enable/disable hw vdev stats
hw_vdev_stats_timer: timer duration for hw vdev stats
Change-Id: I8cbd2b6a7378d8a9e7de920a3a6fdff0cf7785fe
CRs-Fixed: 3067843
In case of WIN hal_soc will be freed in wifi down
path, this pointer is not valid at pdev_detach or
soc_detach.
Change to populate dmac source ring flag to dp_soc
as access is needed at pdev_detach or soc_detach
Change-Id: I628746bdd05ba3791d3d0e6b6dfdf160ed368e9a
Rx patch changes for multichip MLO
1. Create ini for rx ring mask for each chip
2. Configure hash based routing for each chip based
on lmac_peer_id_msb
3. Peer setup changes to configure lmac_peer_id_msb
to enable hash based routing
4. Rx Replenish changes to provide buffers back to owner
SOC of reo ring
Change-Id: Ibbe6e81f9e62d88d9bb289a082dd14b4362252c4
This force use BA64 ini config is no longer needed, because another
gRxAggregationSize can do the same settings and more flexible.
Change is used to remove this config.
Change-Id: Ie780489849f8b701481a628a9bca2b4112460bd8
CRs-Fixed: 3076982
Dynamic GRO feature is enabled by default and aimed for specific
customers. Add an ini control to allow other customers to config
this feature enable/disable.
Change-Id: I7f505599327ac131b3cdac9b4d9e038861b1aeb6
CRs-Fixed: 3074689
This change includes below
1) Changes needed to increase Tx rings to 4
2) Use WBM2SW4 ring for rx error in QCN9224
3) memset srng at alloc to avoid populating RBM_id
in per packet path and enable implicit RBM
Change-Id: Icbd5ac2378273b8f3c6adc41c611e29551fff22f
Currently the IRQ mask for tx completion near full
interrupt is not in sync with the tx completion rings
which are enabled for WCN7850.
Fix the mask for tx completion near full interrupt.
Change-Id: I1432191b260094060873406d48e04fde5b7bc35e
CRs-Fixed: 3052650
Currently, rx packet capture events processing happens even
when feature is disabled by ini. This incurs per packet overhead
in rx path.
The fix is to move all the processing from rx path to packet capture mode
component. Send only wdi event from rx path, when feature is enabled by
ini.
Change-Id: I647256b85117cd3373950c78a5a0ae7d6710e4e2
CRs-Fixed: 2969123
Add support configure ipa tx ring and tx completion ring for
2.4G and/or 5G separately.
Change-Id: Iafb8fa589ff0cce15609a3dfa2209364291d7cef
CRs-Fixed: 2996604
The following configurations are changed
- Change numer of WBM2SWRELEASE rings from 7 to 8
- Use configurable RBM value when enqueuing packets for TX. This is needed
since WBM release ring numbers do not have an easy mapping to RBM values
for HMT1.0.
Change-Id: Idcf9e48e00b7039331fc1837bb1e900b12f19eb3
CRs-Fixed: 2984362
WCN7850 has support for near full indication for
the consumer srngs. This interrupt is used to take
preventive actions to avoid ring full watchdog irq
trigger.
Register for the near full irq and add the necessary
ext groups for these near-full irqs.
Change-Id: Ic16381fceabc54e6c52b34dd13abea74cad4d38c
CRs-Fixed: 2965081
Currently IPA tx buffers are fixed at 1007 buffers.
Adding INI support to change number of TX buffers at load time.
Change-Id: Ide0357554f34759198276b9699e0e6f4a3e20051
CRs-Fixed: 2957916
Provide multiple combinations to configure the msi interrupts
of DP and CE based on the number of MSIs available in the platform.
Number of MSIs used for CE and DP can be changed by modifying the
MSI assignment table in platform driver. Best possible mask for that
MSI is automatically chosen based on predetermined settings.
Change-Id: I02b44fb033631d69d97f2d8d2d3f698541d37aad
In existing implementation, for monitor mode below allocation
are done at pdev attach and init time.
a. 64 monitor buffer allocation for RxDMA monitor buffer ring
b. Link descriptor memory allocation for monitor link descriptor ring
This memory is waste of memory for customers not using monitor mode and
low memory profile.
To optimize this memory, allocate all buffers and link descriptor memory
at monitor vdev creation time.
Change-Id: I873c76d2f625a782532a101037915b0353928a5b
CRs-Fixed: 2829402
