The software mvid/nvid values represent the ratio of mode clock
to link clock. Currently we are converting the link clock to vco
clock, get the ratio of vco clock to mode clock and then adjust
the resulting values to get the ratio of link clock to mode clock.
This change simplifies this logic by directly using the link
clock to get the ratio and uses fixed point arithmetic to scale
the resulting mvid, nvid values to meet requirements.
Change-Id: Ifdfa27edb73d2db6381e592db219e75806d6bdc7
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Modified the pre-emph values for S3P0 & S1P1 in HBR/RBR
table. Also, modified BG timer value as per the latest
HPG changes.
Change-Id: Id9088d3cfe73cb14518dcf490676d92c54925793
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Change removes the dependency of reading MVID and NVID settings
from dispcc registers and calculates the values locally in displayport
driver.
Change-Id: I9ad66aea44a3cbc0f739060c49e23d389022a48a
Signed-off-by: Vara Reddy <quic_varar@quicinc.com>
Swing/Pre-emph, SSC, and CLKBUFLR values updated to match
latest changes as per kalama HPG.
Change-Id: Iae96b38f0f8c39280081ae43b41f73ea10f6ddb7
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Signed-off-by: Vara Reddy <quic_varar@quicinc.com>
Changes include support to update necessary copyright
information to dp file for 4nm target.
Change-Id: Iebb2cc542f7b9262073936f12d55eb1be788e757
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
Changes include updated register writes for DP PLL
as per 4nm target.
Change-Id: I2d8ddbf4af5c2c6d885c73b7c888f31ce45f4cbf
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
Changes include support to correct the version
check for DP PHY changes for 4nm target.
Change-Id: Ib891d43bd5db10edc4b49a70f7a3b8af073167cd
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
Changes include support for specific DP PHY
registers and related code changes for 4nm
target.
Change-Id: I9b349e47ff057421fa465a59e1206fd09f7e367a
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
The offset for DP pixel clock configuration registers in disp_cc has
changed in waipio. Currently the driver is using incorrect offsets to
read M/N values to calculate SW MVID/NVID during MSA programming. This
results in a blank screen as the sink is not able to restore the pixel
clock.
This change fixes this issue by selecting the correct base address
based on dp core version.
Change-Id: I44214ce52c1bc346715362df0a138f1f8cc011e1
Signed-off-by: Sudarsan Ramesh <sudarame@codeaurora.org>
Update the voltage swing and pre-emphasis settings based on the
latest hardware programming guide.
Change-Id: If90db2833aba2bd0613276eff22f850bf34859e5
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Change to update the voltage swing and pre-emphasis settings for
lito to support dp phy cts.
Change-Id: I97f0b9882291d7d52e10ef4bef6ea6a23780e12a
Signed-off-by: Sankeerth Billakanti <sbillaka@codeaurora.org>
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Update the HBR and RBR swing and pre-emphasis levels as per the
latest published hardware programming guide.
Change-Id: If3b6713e0b6680f65539882221aae32b00bf0254
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Currently, for every DP hardware register read/write, there
is a string comparison to determine the execution mode. This
adds up an extra delay while powering up/down which does a
large number of register reads and writes. During stress
testing and automation, this can cause an issue resulting
in failures. Remove the unnecessary delays by using common
APIs for register reads and writes. Switch these APIs only
in case of execution mode change.
Change-Id: I9403873a29b3466c606297b2aa386d0885bb2dc7
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
Change HBR and RBR voltage swing level for 600mV-3.6db
settings on lito/kona as per hardware specification in
dp phy hpg.
Change-Id: If86bf158fb8b538d7ea31364a757584201d5f1c3
Signed-off-by: RAJAT GUPTA <rajatgu@codeaurora.org>
Adding prefixes for error, debug and info
messages in dp files. To enable debug logs
run "echo 0x100 > /sys/module/drm/parameters/debug"
CRs-Fixed: 2493739
Change-Id: Ibf509e837f527be6bff6b7a1c34b0cde2921b388
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Update the DP controller and PHY programming according to
the new hardware recommendations.
CRs-Fixed: 2458753
Change-Id: I1bce5915ba6ebbb250cc5c4aac907b0b287eece7
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
This change brings msm display driver including sde,
dp, dsi, rotator, dsi pll and dp pll from base 4.19 kernel
project. It is first source code snapshot from base kernel project.
Change-Id: Iec864c064ce5ea04e170f24414c728684002f284
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
