Commit graph

249 Commits

Autor SHA1 Nachricht Datum
qctecmdr
bc9f90b65c Merge "disp: msm: sde: reset mixers in crtc when ctl datapath switches" 2021-12-09 05:06:37 -08:00
Jayaprakash Madisetty
8b01e6124e disp: msm: sde: reset mixers in crtc when ctl datapath switches
This change reinitializes the sde_crtc->mixers when CTL
datapath switch occurs during mode set and RM allocation
of CTL hw block is changed. This initialization is required
for CTL_LAYER programming to trigger on the new CTL allocated
from RM.

Issue case:
1. Primary Display is using CTL_0 and it is reserved.
2. Secondary Display is using CTL_1. On suspend, RM adds
   CTL_1 into the free list.
3. External Display is powered on, RM allocates CTL_1 hw blk.
4. Secondary Display is powered on, RM allocated CTL_2 hw blk.
5. External Display is suspended/unplugged, RM adds CTL_1 into
   the free list.
6. When any mode_set(say fps switch) occurs on secondary, RM
   allocates new resources and CTL_1 is allocated.

sde_crtc->num_mixers is non zero, so all the layer programming
happens on CTL_2, but CTL_1_FLUSH bits are programmed causing
hw timeout issue.

Change-Id: I5f1f52b7673740c48b249ab4d36e80b7a1d3db96
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
2021-12-08 11:28:43 +05:30
Yashwanth
b9b744a123 disp: msm: sde: reset CTL_UIDLE_ACTIVE register only if uidle is disabled
This change sets CTL_UIDLE_ACTIVE register whenever uidle
is enabled and resets it only when uidle is disabled.

Change-Id: I0393d1585df4fdb79a844d04df62ac9eda949232
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2021-12-07 14:20:33 +05:30
qctecmdr
ae1d2e9c54 Merge "disp: msm: sde: deprecate idle notify work scheduling" 2021-11-20 00:19:10 -08:00
qctecmdr
80a394d31a Merge "disp: msm: sde: update uidle_db_updates in both enable/disable cases" 2021-11-17 01:00:40 -08:00
Raviteja Tamatam
d098764f5b disp: msm: sde: update uidle_db_updates in both enable/disable cases
uidle_db_updates are generated when CTL_x_UIDLE_ACTIVE is set to 1.
It needs to enabled in both uidle enable and disable cases.
CTL_x_UIDLE_ACTIVE is set to 0 only in cases where uidle configuration
is not updated.

Change-Id: If7655e4eae351bac248f0906c473cdfaf93f2b8a
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2021-11-15 13:12:58 -08:00
Yashwanth
a5382aff7e disp: msm: sde: deprecate idle notify work scheduling
This change deprecates idle notify work for video mode
since idle timer will be maintained by userspace.
As part of idle notify work, syscache state is changed from
CACHE_STATE_NORMAL to CACHE_STATE_PRE_CACHE along with
notifying to the userspace. This change removes
CACHE_STATE_PRE_CACHE in the state machine and state is
updated from CACHE_STATE_NORMAL to CACHE_STATE_FRAME_WRITE
whenever the cache property is set.

Change-Id: If3b2c34be954cb625aca76da81fd854c077a8250
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2021-11-11 11:07:54 +05:30
Abhijit Kulkarni
683f6bc6af disp: msm: sde: send event on trusted vm transition
This change sends a notification to user mode after msm_drm
driver releases the mmio and irq resources on trusted vm transition
request. This is required as user mode has no other way to know
when the resources where actually released. User mode driver earlier
relied on retire fence signaling but retire fences are send before
releasing the hw.

Change-Id: Ia218cfcbf398b2de1ad9578fb9baedf348b067df
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2021-11-04 11:45:25 -07:00
Ping Li
4d27e37beb disp: msm: sde: add new function for updating the cp feature lists only
When sde_crtc_atomic_begin is called before crtc is enabled, all the
color processing features need to be moved from active_list to
dirty_list after sde_cp_crtc_apply_properties(). However, the
ltm_hist_en flag doesn't need to be set to false in this case.
Setting ltm_hist_en to false in this case will result LTM merge_en bit
being cleared incorrectly. This change replaces sde_cp_crtc_suspend()
with a new function that only updates the color processing feature lists
in sde_crtc_atomic_begin().

Change-Id: I75d7874899838855bda05a1e8eca0cb9523417e9
Signed-off-by: Ping Li <pingli@quicinc.com>
2021-10-20 11:16:56 -07:00
Dhaval Patel
c281b3a879 disp: msm: reserve core clock rate during display disable
Userspace module may not trigger the atomic check and it
can cause the commit failure. In such case, always reserve
the minimum core clock rate on mmrm module for built-in
displays to avoid the power ON failure.

Change-Id: Iafd92a7b7d1b35befe70b041cbedaec2add40de4
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2021-09-27 13:44:12 -07:00
Dhaval Patel
fc2226ea25 disp: msm: reset lm blend stages for missing vsync
MDSS INTF HW block does not generate vsync if controller
turns off the link clock prematurely. This leads to
frame trigger timeout and SDE driver triggers the retire
fence after 84ms to recover gracefully. A client may switch
source pipe from one CTL path to another CTL path based
on delayed retire fence. It can lead to other ctl path
hang. This can be resolved by resetting the lm blend
stages for each missing vsync frame trigger.

Change-Id: I5a6ed03afbdad83d8fd6decc593d39e04bef62e4
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2021-09-22 09:46:32 -07:00
qctecmdr
bb36f9fd40 Merge "disp: msm: sde: add helper to check VM hw availability" 2021-08-18 16:48:48 -07:00
Steve Cohen
7f3b2f0a4b disp: msm: sde: add helper to check VM hw availability
Add a utility function to check if HW has been handed over to
another VM.

Change-Id: Ic36ca1e7f15f7608e69d69fc3f4e7ad40be15704
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2021-08-12 22:58:30 -04:00
Prabhanjan Kandula
642c86fee9 disp: msm: sde: compute timeouts based on refresh rate
Current timeout values in sde driver for vblank, kickoff and
frame complete timeouts are fixed and can be much lower than
a vsync incase of low refresh rate display. Compute timeouts
based on refresh rate for low refresh rate displays.

Change-Id: I9dda41feb15446de7451824e185321de421ad575
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
2021-08-10 14:51:41 -07:00
Amine Najahi
0c8c956b1f disp: msm: sde: expose number of rounded corner blocks
Expose the number of RC hardware blocks to handle multi-display
use cases where RC feature needs to be enabled only if there
are sufficent RC hardware blocks available.

Change-Id: I37fe3ee4ac72894d9d51e832551d3fc19c0354b8
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
2021-07-29 15:10:24 -04:00
Steve Cohen
a42fd877c7 disp: msm: sde: cancel delayed work items during TUI transition
Delayed work items may touch HW registers. If these work items
run while HW is not owned by this VM it will lead to invalid
access. This happens in video mode as HAL does not disable idle
power-collapse in this mode. It can also happen with ESD status
if lastclose or TUI transition failure occurs.

Although there is a contract with user mode to turn off certain
features, kernel cannot rely on it to always do the right thing.
Prevent potential crashes from certain corner cases by
cancelling all delayed work items when the HW ownership is
transferred.

Change-Id: I08da17f2ce72bf2fddf71924c3e8edd2e2715be8
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2021-07-16 20:45:42 -04:00
qctecmdr
a5da9d0045 Merge "disp: msm: sde: remove fb's attached to a drm_file in preclose" 2021-07-15 13:14:46 -07:00
qctecmdr
a44120edf1 Merge "disp: msm: sde: correct num_datapath during PM resume with CWB" 2021-07-15 13:14:46 -07:00
qctecmdr
e32c87abbe Merge "disp: msm: sde: modify in_clone_mode after wb_reset is done" 2021-07-15 13:14:46 -07:00
Jayaprakash Madisetty
436efb403c disp: msm: sde: modify in_clone_mode after wb_reset is done
Add changes to modify the phys_enc->in_clone_mode variable
post wb_reset_state since this is a shared variable used
during atomic_check and atomic_commit. In current issue case,
wb_atomic_check has set in_clone_mode to true in commit N,
and in commit N-1 CWB is being disabled and re-sets the
in_clone_mode variable to false causing pp_done timeouts in
primary in commit N.

Change-Id: I8159bbdb5622a351d76bdc4dba75d48df20f4365
Signed-off-by: Jayaprakash Madisetty <jmadiset@codeaurora.org>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2021-07-14 13:43:21 -07:00
Jayaprakash Madisetty
a29369e224 disp: msm: sde: correct num_datapath during PM resume with CWB
In PM resume with CWB concurrency usecase, crtc pointer in
conn->state is NULL since drm_mode_config_reset operation is
performed on pm_resume. This change relies on conn_mask in
new_crtc_state for primary connector retrieval and also adds
get_num_lm_from_mode callback to DSI for LM count retrieval
from dsi panel topology. Existing get_mode_info api cannot
retrieve the topology info because mode->priv_info is NULL.
This occurs as WB encoder is added in the drm encoder_list
before primary encoder, introduced as part of commit d28ebf05f4
("disp: msm: sde: populate WB display encoder list before dsi").

Change-Id: I55358fd88ab778bd81475cf3628be13335de1cb5
Signed-off-by: Jayaprakash Madisetty <jmadiset@codeaurora.org>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2021-07-09 09:12:26 -07:00
Yashwanth
ddd671b0d7 disp: msm: sde: reset dim layer dirty prop during idle pc
During idle power collapse, dim layer dirty flags are
stored in sde_crtc_state which might be invalid if state
swap occurs. This change adds revalidate mask in sde_crtc
structure to revalidate after coming out of idle power
collapse.

Change-Id: Ie2f34a794896a3f8e729ef7d1f3ae35340123257
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2021-07-08 10:24:48 -07:00
Jayaprakash Madisetty
0e3d422520 disp: msm: sde: remove fb's attached to a drm_file in preclose
This change avoids upstream drm issuing drm_atomic_commit in
drm_fb_release which is leading to artifacts on screen or
atomic_check failures due to atomically unstaging each fb
from plane_state and committing remaining planes on hardware.

 a) This patch moves the state operations for setting crtc to
    connector state to a helper api.
 b) This patch clears any dim_layers present in the crtc_state
    as part of null commit.
 c) This patch removes any framebuffers attached to a drm_file
    in msm_preclose whose refcount is not managed by composer kill
    inadvertently and issues null flush to hardware in such cases.
 d) This patch handles msm_preclose as part of msm_release
    operation since legacy feature is not supported
    for msm_driver.

Change-Id: Ib2068d74d4b23b73b7c84544858c9f6bb6adfa67
Signed-off-by: Jayaprakash Madisetty <jmadiset@codeaurora.org>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2021-07-08 10:24:32 -07:00
qctecmdr
6a01182c1e Merge "disp: msm: sde: update max_dp_dsc_count in dsc switch case" 2021-07-07 01:25:31 -07:00
Samantha Tran
9d67c9da7a disp: msm: sde: do not expose Demura CWB tap point capability
This change removes exposing Demura CWB tap point capability
to userspace.

Change-Id: I7be24a2004ce489fca76593cdb9f75e8b52d4461
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2021-06-21 15:21:19 -07:00
Raviteja Tamatam
9a96017f9a disp: msm: sde: update max_dp_dsc_count in dsc switch case
max_dp_dsc_count needs to be updated to total dsc count
only if dsc_switch_support is present. Updated
allowed_dsc_reservation_switch just after connector_init
before max_dp_dsc_count value is modified.

Change-Id: I878cde62b4940c629293eba0a3794f4dc2996b4f
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
2021-06-08 20:07:26 +05:30
qctecmdr
8bbc6f2698 Merge "disp: msm: sde: flush commit thread queue during pm suspend" 2021-06-01 20:21:34 -07:00
qctecmdr
ffe21ad278 Merge "disp: msm: sde: fix indexing for frame data" 2021-05-31 08:46:29 -07:00
Linux Build Service Account
deef47dba0 Merge "disp: msm: sde: avoid mixer op setup for virtual LM" into display-kernel.lnx.5.10 2021-05-21 10:05:11 -07:00
Raviteja Tamatam
3789258773 disp: msm: sde: add allowed_dsc_reservation_switch capability
This change adds allowed_dsc_reservation_switch to determine if
dsc seamless switch is supported for DP. Also, based on the
flag, it determines and populates the required number of
available resources for DP.

Change-Id: I9cd7219a50d352369c5bc8386ce7dc25c30b80b6
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
2021-05-20 21:36:05 -07:00
Samantha Tran
ef2525e0cc disp: msm: sde: avoid mixer op setup for virtual LM
This change sets a flag to true if a mixer is a virtual mixer.
Virtual mixers will skip setting up mixer ops and debug register
dumps as their range is not valid. Since mixer ops are no longer
guaranteed to be set, add null checks before using these ops.

Change-Id: Idfe7e1e2b893dadbbe6756d69d0c4ca4fa6ae4ce
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2021-05-19 19:35:00 -07:00
Andhavarapu Karthik
78b4029179 disp: msm: sde: allow input fence status show only when kickoff in progress
Allow input fence status read only when crtc kickoff is in
progress to avoid race between status read and fence destroy.

Change-Id: I3402bfcb38940628f09f645a3cee31f821daeae9
Signed-off-by: Andhavarapu Karthik <kartkart@codeaurora.org>
2021-05-19 16:35:40 -04:00
Yashwanth
75f3403326 disp: msm: sde: add kickoff_in_progress flag in sde crtc
In dual display usecases, during pm suspend/resume,
commit is scheduled only on primary crtc thread. If idle
timeout value is very short such as in LP2 mode, it might
result in race condition due to idle pc off work getting
scheduled on its crtc thread. This change adds kickoff in
progress flag to handle such cases as crtc frame pending
count is only updated after rc kickoff.

Change-Id: Iebb331d914b23cc5eeadfeb2a488891e88b3202a
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2021-05-19 16:35:40 -04:00
Yashwanth
4f8792dfc6 disp: msm: sde: perform only soft reset during timeout scenarios
During wait for commit done failure cases in the current
code in video mode and command mode(posted start), global
atomic state for current crtc state will be assigned NULL
during state swap which will lead to crash while using
drm_atomic_crtc_state_for_each_plane API. Also in such
timeout cases, border color staging and kickoff being
done without any vblank wait might lead to inconsistent
state because of configuration overriding from the next
commit. Since the timeout is observed at the end of commit
cycle, only soft reset should be done here and remaining
in the next commit cycle.

Change-Id: I0d42dc27035f4f79394aeec347d797c99ed76e5f
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2021-05-19 16:35:40 -04:00
Yashwanth
8e53d758dd disp: msm: sde: add ctl reset during wait for commit done timeout
During one of the DP timeout usecases, flush doesn't take
effect due to vid vblank wait failure. As a result, smmu
faults are observed because of fetching the previously
staged planes. This change adds ctl reset in the same
DP atomic commit context to recover and avoid
smmu faults.

Change-Id: I2f9aceca56e27f140607317f7596d6fe0d908af8
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2021-05-19 16:35:40 -04:00
Yashwanth
e96e5bd074 disp: msm: sde: add pending ctl recovery mask in sde_kms
This change adds pending ctl recovery mask in sde kms
structure to check if there are any ctl paths pending
for recovery and stages only border fill during such
conditions to avoid device crash. Below is the issue
sequence observed during the crash:

1) On one of the ctl path, flush didn't take effect and
flush bits are still pending.

2) It was a NULL flush and last good flush on that
interface has DMA2 pipe staged along with other pipes.

3) Different ctl path re-uses the DMA2 pipe (attached to
ctl path in #1) causing wr_ptr timeout followed by
ppdone timeout.

Change-Id: I07eb9f2fe41f59963dc27655c551c05abe240392
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2021-05-19 16:35:40 -04:00
Nilaan Gunabalachandran
cd77cb672d disp: msm: sde: fix indexing for frame data
This change adds a fix to correct indexing logic while
parsing frame data buffers and resets the count correctly.

Change-Id: Ic5a20ecd7093423ea293432c9492eb920acdd6f4
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2021-05-18 17:12:46 -04:00
Anjaneya Prasad Musunuri
163b57e6a8 disp: msm: sde: correct noise and attenuation layers blend stages
Use blend stage to get blend offset instead of z order.

Change-Id: I7924325d19dfbace0fadf4551f696fe222d17115
Signed-off-by: Anjaneya Prasad Musunuri <aprasad@codeaurora.org>
2021-05-04 06:18:38 -07:00
Samantha Tran
0bcdb28eda disp: msm: sde: allow exclusively updating Connector ROI in clone mode
While in clone mode, allow connector ROI property to be set without
setting CRTC ROI property. Currently, both these properties must be
set or else an error is reported.

Change-Id: I516c27a3d31c8d31b967e4c8577f57f1b8b7e327
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2021-04-30 13:07:26 -07:00
Christopher Braga
a1698f39de Revert "disp: msm: sde: reprogram crtc and planes after post enable power event"
This reverts commit e2b438d88b.

Change-Id: I6d593121e74110fbe790ae4624a1c5df1b1ec731
Signed-off-by: Christopher Braga <cbraga@codeaurora.org>
2021-04-21 16:55:45 -04:00
qctecmdr
65ec8c0551 Merge "disp: msm: sde: reprogram crtc and planes after post enable power event" 2021-04-07 21:41:27 -07:00
Tatenda Chipeperekwa
e2b438d88b disp: msm: sde: reprogram crtc and planes after post enable power event
This change reprograms planes and crtc as part of the post enable
power event so that the first commit sequence after this event
does not have to reprogram these.

Change-Id: I2403337b95c70d2a3104aefcc647afa66f4c69a6
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2021-04-06 09:03:16 -07:00
Nilaan Gunabalachandran
c5835a215e disp: msm: sde: frame data feature
Add support to send a data packet of info, written to
predefined buffers, providing information about each submitted frame.
Add required UAPI definitions for frame data buffers and event
notification.
Add support to read ubwc statistics from hw, based on defined rois.

Change-Id: I51f279de98ae4e2a02b0df6943d334764011d5db
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2021-04-06 08:49:49 -04:00
qctecmdr
044fa60dd8 Merge "disp: msm: sde: expose skip inline rot threshold property" 2021-04-03 05:48:59 -07:00
qctecmdr
a8bdcf2e77 Merge "disp: msm: sde: report AVR_STATUS in vsync_event sysfs node" 2021-04-02 17:42:22 -07:00
Samantha Tran
b2e26167dc disp: msm: sde: expose skip inline rot threshold property
This change exposes whether or not inline rotation threshold
should be taken into consideration or skipped based on
skip_inline_rot_threshold property.

Change-Id: I4108f6ae86039815d28836bfa0e184737aaddd8a
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2021-04-02 10:09:13 -07:00
qctecmdr
b0d2030f38 Merge "display: msm: sde: update qos lut after scaler config" 2021-04-01 22:56:00 -07:00
Abhijit Kulkarni
559620308e display: msm: sde: update qos lut after scaler config
This change moves the code of updating the qos lut for qseed3
to each plane after updating the scaler configuration. This
avoids using stale values for qos settings.

Change-Id: I2c55a98e1ba9790d596c55160933cd5afd2388e5
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2021-03-31 17:32:30 -07:00
Narendra Muppalla
21f527d47d disp: msm: sde: use different spin lock for frame events
Due to lock sequence inconsistency between sde_crtc->spin_lock and
sde_kms->hw_intr->irq_lock can cause deadlock, to avoid this possible
deadlock this change uses different spin lock for frame events.

Change-Id: I51b1184dfa1069c87653099b95b992b277721daf
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
2021-03-31 15:02:14 -07:00
Veera Sundaram Sankaran
d26e510b77 disp: msm: sde: avoid sde debugfs register access based on HW ownership
Add VM ownership checks before accessing the HW through the debugfs
path in sde crtc/encoder/connector modules to avoid illegal access.

Change-Id: I4ff8f29353835d263beb2091bdeec40125addbf8
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
2021-03-31 14:56:57 -07:00