The divider value for vco clock is only dependent on the link rate
and is known during pll configure. Instead of depending on the
clock framework to program this divider as part of stream clock
enable, this change moves the configuration to pll configuration
and removes the set rate call on the vco clock.
Change-Id: If687a8ab057fdfd6c3b3ad2bd1c51663d9182ff4
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
With the change in the clock names for newer targets, this fix
updates the driver to support different clock names per target.
Change-Id: I58c35fce34356f8c79adb0ac8a907e2fb60813ae
Signed-off-by: Sudarsan Ramesh <sudarame@codeaurora.org>
The current pll driver models the entire DP clock
hierarchy using the clock framework. This creates
unnecessary dependency between the dp driver and
the clock driver and also limits the flexibility
to dp driver when configuring the DP clocks.
This change models these clocks as single nodes
and provide full control to the dp driver and
also minimizes the dependency on the clock driver.
Change-Id: Id5221441ea33b576e7c543396a12cbeb7b44d319
Signed-off-by: Yuan Zhao <yzhao@codeaurora.org>
Add support for PLL programming in the DisplayPort driver.
Change-Id: I4f08a621dcae5d1f54d67bb5c34409249012cc7b
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
