This patch overrides the fal10 veto for the milos target.
Change-Id: I82310b63ff89aa44c03b97e4e7b6e87ac5c4569a
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
Add changes to include qseed inefficiency factor during mdp
core clock calculation. This calculated value is sent to
mmrm driver to set with reserve only flag.
Change-Id: If19356ba36e7f9155fdfeeadead9260d1c56dc6b
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
This change enables the uidle feature support for milos target.
Change-Id: I3f8633b623d69467010639b48e47a2455f64c55b
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
In DP simulation mode, DP link clock's parent is driven
by usb pll clock, in case usb is disconnected during
DP simulation, those registers driven by DP link clock
cannot be accessed any more. In that case, put xo clock as
DP link clock's parent to keep the registers driven by
link clock still be accessible.
Change-Id: I2bbe6b92052284c7825f80348818d00557312a10
Signed-off-by: Yu Wu <quic_zwy@quicinc.com>
As part of partial update, the DSI command engine is programmed
with the new ROI. However, because double buffering is not enabled
for DSI command mode registers, updating them during a partial
update use case when the previous frame is not yet finished can
result in a configuration mismatch between MDP and DSI. In this
scenario, DSI is configured with the new ROI, while MDP is still
configured for the previous frame’s ROI. This mismatch can lead
to a write pointer timeout.
To avoid this issue, wait for MDP to be idle before updating the
new ROI.
Change-Id: I1796cb7872edaf9e1d76681c2d948bc1b567c298
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
When there is CWB enablement + dynamic clock change request in
single commit, during modeset enables the cwb seamless check
is hit for primary connector causing bridge pre enable
and enable calls skipped for dsi connector. This change ensures
the above seamless transition is taken care with any modeset case
as well.
Change-Id: I8d7ef4f8c579d44ddb0bfd5dc584fe5c778df886
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
We currently wait for the completion of previous ASYNC command
transfers on a controller before initiating a new command transfer
on that controller. However, in the case of split DSI usage, the
controllers can encounter issues if a unicast command transfer
occurs before the previous broadcast is complete on both controller.
To prevent this issue, it’s required to flush the CMD DMA of both
controllers before initiating the unicast command transfer following
a previous broadcast.
Change-Id: If2830bea81e32ab26d3b91754bcdf047c3cba483
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
Print sgl entries to aid debugging if sgl validation fails
due to mismatch of assigned and expected resources entry.
Change-Id: I63c7ad3a716d3fa37c886f29fa0ac7af6f960aaf
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
Color features are disabled during encoder disable, but reg dma
flush is not triggered. This change does reg dma flush for the
features to be disabled during encoder disable.
Change-Id: Ia74d4c43ad7b699f0097b49d86ad59529c0b3230
Signed-off-by: Anjaneya Prasad Musunuri <quic_aprasad@quicinc.com>
This change checks for hdr capability of connected receiver based on
vsc support of the same. If vsc support is not present, the parsing of
hdr extented block is avoided.
Change-Id: I5db5d1fe3e287123241ade10b698bb32f430ec43
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
Add changes to wait for hwactive jobs to be kicked off and
receive done interrupt from rotator hw during rotator
session close. Only cancel rotator jobs which are
assigned but not kicked off on rotator hw.
Change-Id: Id7671370148ae0f01de8e0a47ae2896d234226b0
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
When partial fb is sent from userspace to dump only partial
frame roi, cwb crop feature needs to be enabled.
'commit fded005881
("disp: msm: sde: add support for CWB + single LM partial update")'
is overriding this crop ctrl enable bit. Due to this cwb xin is idle
always and wb timeouts are seen. Add changes to move the cwb setup
with false to happen early to fix overriding the crop ctrl enablement.
Change-Id: If187319d59026f43db71e6655a74bfd62acf2dc3
Signed-off-by: Akhil Jaiswal <quic_akhijais@quicinc.com>
Add changes to update the register_dump_range offset_start and
offset_end validation introduced as part of 'commit cfc54d3f22
("disp: msm: sde: add check to avoid registering invalid ranges in dump")'.
Change-Id: I5e4332687b37d7926afdce6903d8fea6ce2874b1
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Move DP disconnect process to DP work queue to fix DP
notification issue when disconnecting USB cable.
Change-Id: Ib864563f35012ae4499ca5e3002eb52d1084ae58
Signed-off-by: Yahui Wang <quic_yahuiw@quicinc.com>
During Link CTS test, it is possible that the TE would trigger an HPD
IRQ right after LT. Currently we are waiting for a fixed delay before
sending connect notification to usermode, so that the driver can
process any attention work queue requests immediately. This change
checks for any pending attention work queue requests before waiting
for timeout. After the attention work is done with any test request,
TE can trigger an unplug before running the next test case. In the
current flow we send HPD notification at the end of the attention
work without checking the HPD status, leading to delay in processing
the test requests. Rectified here.
Change-Id: I600c69abfc31deee25e09756c73592854e3faa3b
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
This change avoids the enabling or disabling of vblank for
virtual displays. It ensures that vblank remains disabled
regardless of userspace requests.
Change-Id: I104cae9b8c0c4770b5092df49bd30501b09cbbc7
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
Update max value for brightness property during property install.
In dual display with different max brightness level, property install
happens for primary display with its max value. When there is brightness
update for secondary display then it will fail in check for set property
due comaparison with max brightness of primary display. Avoid this by
updating max value of brightness property to 0xFFFF.
Change-Id: Icb6f19312075670f228d371b15a1a81dffaab341
Signed-off-by: Anand Tarakh <quic_atarakh@quicinc.com>
Some panels need at least one frame to be transferred to GRAM
before enabling the backlight. This is done by delaying the
backlight update to these panels until the first frame commit
is completed. This feature is activated by setting the
"qcom,bl-update-flag = delay_until_first_frame" property in the
device tree. However, this feature adds delay in the POMS
(video 2 command) use case adversely. To address this additional
delay, avoid delaying the backlight for the POMS use case.
Change-Id: Ia25afd35f9fe4ffa7d56bddad2f0975a77f39fdf
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
In trusted vm, a stub function is used for the panel_ops.bl_register,
hence the backlight_device bl->raw_bd used for WLED backlight type
remains uninitialized.
If the panel backlight is WLED, this can cause a NULL pointer
dereference in TVM during dsi_panel_bl_handoff().
Add a check before dereferencing bl->raw_bd.
Change-Id: Ieb40781263b4318313fd29b339122ae6c59b1590
Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com>
Add property to parse the ddr type and select the vbif QOS
values based on the detected ddr type.
Change-Id: Ifc980b5bdadc38b7b0882568a1f07e4e8441303a
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
Signed-off-by: Akhil Jaiswal <quic_akhijais@quicinc.com>
Ensure to allocate switch type as bypass in case of dp aux switch
node missing in device tree entry and prevent any scope of null
pointer dereferencing.
Change-Id: I1d50d785e028f2e69a0effaedb2dbb6568a473dd
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
This change fixes the 'commit 92cbd6d654 ("disp: msm: sde: while
timing engine enabling poll for active region")' which introduces
one frame time delay during enabling the timing engine.
Change-Id: Ibe71eb785822381fd23e74f4d55dbd141024d520
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
Add changes to support odd number of dedicated-CWB.
Change-Id: I21c8521e98f6a8b5bb002f1c056afc501e7e9780
Signed-off-by: Akhil Jaiswal <quic_akhijais@quicinc.com>
When enable spr 2d filer in PU case, The extra line will be over
fetch on top of roi. But for demura, it does not require over fetch.
Theresfore the height of demura plane is not same with the height
of LM.
Change modify the checking on height while set demura config.
Change-Id: Ie2232e0cd6ea0bec366a1f44b556cc13502cb512
Signed-off-by: Qing Huang <quic_huangq@quicinc.com>
In Commit N, llcc is enabled. However in Commit N+1, suspend
is triggered without a llcc disable commit. As a result, llcc
remains active, preventing ADSP from entering the island.
Change-Id: I36fd8cc8c3f8a97e18b53507749a1b639f0c0cfd
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
