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@@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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- * Copyright (c) 2021-2023, Qualcomm Innovation Center, Inc. All rights reserved.
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+ * Copyright (c) 2021-2024, Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved.
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*/
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@@ -33,6 +33,7 @@ struct dp_power_private {
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bool strm1_clks_on;
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bool strm0_clks_parked;
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bool strm1_clks_parked;
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+ bool link_clks_parked;
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};
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static int dp_power_regulator_init(struct dp_power_private *power)
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@@ -316,6 +317,9 @@ static int dp_power_park_module(struct dp_power_private *power, enum dp_pm_type
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} else if (module == DP_STREAM1_PM) {
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clk = power->pixel1_clk_rcg;
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parked = &power->strm1_clks_parked;
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+ } else if (module == DP_LINK_PM) {
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+ clk = power->link_clk_rcg;
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+ parked = &power->link_clks_parked;
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} else {
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goto exit;
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}
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@@ -340,7 +344,7 @@ static int dp_power_park_module(struct dp_power_private *power, enum dp_pm_type
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goto exit;
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}
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- mp->clk_config->rate = XO_CLK_KHZ;
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+ mp->clk_config->rate = XO_CLK_KHZ * 1000;
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rc = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk);
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if (rc) {
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DP_ERR("failed to set clk rate.\n");
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@@ -494,6 +498,8 @@ static int dp_power_clk_enable(struct dp_power *dp_power,
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power->strm0_clks_parked = false;
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if (pm_type == DP_STREAM1_PM)
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power->strm1_clks_parked = false;
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+ if (pm_type == DP_LINK_PM)
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+ power->link_clks_parked = false;
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/*
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* This log is printed only when user connects or disconnects
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@@ -707,6 +713,12 @@ static int dp_power_park_clocks(struct dp_power *dp_power)
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goto error;
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}
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+ rc = dp_power_park_module(power, DP_LINK_PM);
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+ if (rc) {
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+ DP_ERR("failed to park link clock. err=%d\n", rc);
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+ goto error;
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+ }
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+
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error:
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return rc;
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}
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