As per HW recommendation, FAL10_VETO_OVERRIDE register can
be programmed to disable FAL10 in alternate to disabling
uidle at the sspp level as disabling UIDLE controller will
only disable DPU traffic shaping and will not stop the
system from entering FAL10 state. This change programs
FAL10_VETO_OVERRIDE register during uidle disable and also
sets CTL_x_UIDLE_ACTIVE register to always one to avoid
race condition between different CTL paths.
Change-Id: I9c55f5da2037cb8c448cc978eac0a04608a93650
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
Add support for the option to enable microidle FAL1 only setting.
Previously microidle enabled would automatically have both
FAL1 and FAL10. Now in cases of higher FPS or DFPS we can
choose to enable FAL1. This change also adds qos recommended
waipio target specific fps limits for fal1 and fal10.
Change-Id: I7aa7d003afc3ac77c671b2467b0e6dedaae772aa
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
This change adds the hooks to enable the active signal override
in power collapse sequence. Active signal override is needed to
disable the clock gating when the power collapse sequence
is running.
Change-Id: I9edaed7960b236b3d0179cb67f9cc2c9b3546c9d
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Print uidle status fal10 enable bit as part of checking status.
Change-Id: Ibe00216ac22bb31fbe0925db3abc1d5dc4371ad3
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
This change brings msm display driver including sde,
dp, dsi, rotator, dsi pll and dp pll from base 4.19 kernel
project. It is first source code snapshot from base kernel project.
Change-Id: Iec864c064ce5ea04e170f24414c728684002f284
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
