disp: msm: sde: enable FAL1 only option for microidle

Add support for the option to enable microidle FAL1 only setting.
Previously microidle enabled would automatically have both
FAL1 and FAL10. Now in cases of higher FPS or DFPS we can
choose to enable FAL1. This change also adds qos recommended
waipio target specific fps limits for fal1 and fal10.

Change-Id: I7aa7d003afc3ac77c671b2467b0e6dedaae772aa
Signed-off-by: Samantha Tran <[email protected]>
Signed-off-by: Prabhanjan Kandula <[email protected]>

msm/sde/sde_core_perf.c

@@ -491,13 +491,13 @@ static void _sde_core_uidle_setup_wd(struct sde_kms *kms,
 }
 
 static void _sde_core_uidle_setup_cfg(struct sde_kms *kms,
-	bool enable)
+	enum sde_uidle_state state)
 {
 	struct sde_uidle_ctl_cfg cfg;
 	struct sde_hw_uidle *uidle;
 
 	uidle = kms->hw_uidle;
-	cfg.uidle_enable = enable;
+	cfg.uidle_state = state;
 	cfg.fal10_danger =
 		kms->catalog->uidle_cfg.fal10_danger;
 	cfg.fal10_exit_cnt =
@@ -507,7 +507,7 @@ static void _sde_core_uidle_setup_cfg(struct sde_kms *kms,
 
 	SDE_DEBUG("fal10_danger:%d fal10_exit_cnt:%d fal10_exit_danger:%d\n",
 		cfg.fal10_danger, cfg.fal10_exit_cnt, cfg.fal10_exit_danger);
-	SDE_EVT32(enable, cfg.fal10_danger, cfg.fal10_exit_cnt,
+	SDE_EVT32(state, cfg.fal10_danger, cfg.fal10_exit_cnt,
 		cfg.fal10_exit_danger);
 
 	if (uidle->ops.set_uidle_ctl)
@@ -529,19 +529,21 @@ static void _sde_core_uidle_setup_ctl(struct drm_crtc *crtc,
 }
 
 static int _sde_core_perf_enable_uidle(struct sde_kms *kms,
-	struct drm_crtc *crtc, bool enable)
+	struct drm_crtc *crtc, enum sde_uidle_state uidle_state)
 {
 	int rc = 0;
+	bool enable = (uidle_state > UIDLE_STATE_DISABLE);
 
-	if (!kms->dev || !kms->dev->dev || !kms->hw_uidle) {
-		SDE_ERROR("wrong params won't enable uidlen");
+	if (!kms->dev || !kms->dev->dev || !kms->hw_uidle ||
+			uidle_state >= UIDLE_STATE_ENABLE_MAX) {
+		SDE_ERROR("wrong params won't enable uidle_state %d\n", uidle_state);
 		rc = -EINVAL;
 		goto exit;
 	}
 
-	SDE_EVT32(enable);
+	SDE_EVT32(uidle_state);
 	_sde_core_uidle_setup_wd(kms, enable);
-	_sde_core_uidle_setup_cfg(kms, enable);
+	_sde_core_uidle_setup_cfg(kms, uidle_state);
 	_sde_core_uidle_setup_ctl(crtc, enable);
 
 	kms->perf.uidle_enabled = enable;
@@ -596,7 +598,7 @@ void sde_core_perf_crtc_update_uidle(struct drm_crtc *crtc,
 {
 	struct drm_crtc *tmp_crtc;
 	struct sde_kms *kms;
-	bool disable_uidle = false;
+	enum sde_uidle_state uidle_status = UIDLE_STATE_FAL1_FAL10;
 	u32 fps;
 
 	if (!crtc) {
@@ -621,6 +623,8 @@ void sde_core_perf_crtc_update_uidle(struct drm_crtc *crtc,
 	}
 
 	drm_for_each_crtc(tmp_crtc, crtc->dev) {
+		enum sde_uidle_state uidle_crtc_status = UIDLE_STATE_FAL1_FAL10;
+
 		if (_sde_core_perf_crtc_is_power_on(tmp_crtc)) {
 
 			/*
@@ -638,19 +642,29 @@ void sde_core_perf_crtc_update_uidle(struct drm_crtc *crtc,
 				tmp_crtc->base.id, fps,
 				_sde_core_perf_is_wb(tmp_crtc),
 				_sde_core_perf_is_cwb(tmp_crtc),
-				disable_uidle, enable);
+				uidle_status, uidle_crtc_status, enable);
 
 			if (_sde_core_perf_is_wb(tmp_crtc) ||
-				_sde_core_perf_is_cwb(tmp_crtc) || (!fps ||
-				 fps > kms->perf.catalog->uidle_cfg.max_fps)) {
-				disable_uidle = true;
+				_sde_core_perf_is_cwb(tmp_crtc) || !fps) {
+				uidle_status = UIDLE_STATE_DISABLE;
 				break;
 			}
+
+			/* Check if FAL1 only should be enabled */
+			if (fps <=  kms->perf.catalog->uidle_cfg.max_fps)
+				uidle_crtc_status = UIDLE_STATE_FAL1_FAL10;
+			else if (fps <= kms->perf.catalog->uidle_cfg.max_fal1_fps)
+				uidle_crtc_status = UIDLE_STATE_FAL1_ONLY;
+
+			if (uidle_crtc_status == UIDLE_STATE_DISABLE)
+				break;
+			else if (uidle_crtc_status < uidle_status)
+				uidle_status = uidle_crtc_status;
 		}
 	}
 
 	_sde_core_perf_enable_uidle(kms, crtc,
-		(enable && !disable_uidle) ? true : false);
+			enable ? uidle_status : UIDLE_STATE_DISABLE);
 
 	/* If perf counters enabled, set them up now */
 	if (kms->catalog->uidle_cfg.debugfs_perf)

msm/sde/sde_hw_catalog.c

@@ -155,6 +155,8 @@
 #define SDE_UIDLE_MAX_DWNSCALE 1500
 #define SDE_UIDLE_MAX_FPS_60 60
 #define SDE_UIDLE_MAX_FPS_90 90
+#define SDE_UIDLE_MAX_FPS_120 120
+#define SDE_UIDLE_MAX_FPS_240 240
 
 #define SSPP_GET_REGDMA_BASE(blk_base, top_off) ((blk_base) >= (top_off) ?\
 		(blk_base) - (top_off) : (blk_base))
@@ -4789,7 +4791,8 @@ static void _sde_hw_setup_uidle(struct sde_uidle_cfg *uidle_cfg)
 	if (!uidle_cfg->uidle_rev)
 		return;
 
-	if ((IS_SDE_UIDLE_REV_101(uidle_cfg->uidle_rev)) ||
+	if ((IS_SDE_UIDLE_REV_102(uidle_cfg->uidle_rev)) ||
+			(IS_SDE_UIDLE_REV_101(uidle_cfg->uidle_rev)) ||
 			(IS_SDE_UIDLE_REV_100(uidle_cfg->uidle_rev))) {
 		uidle_cfg->fal10_exit_cnt = SDE_UIDLE_FAL10_EXIT_CNT;
 		uidle_cfg->fal10_exit_danger = SDE_UIDLE_FAL10_EXIT_DANGER;
@@ -4809,6 +4812,13 @@ static void _sde_hw_setup_uidle(struct sde_uidle_cfg *uidle_cfg)
 			uidle_cfg->fal10_threshold =
 				SDE_UIDLE_FAL10_THRESHOLD_90;
 			uidle_cfg->max_fps = SDE_UIDLE_MAX_FPS_90;
+		} else if (IS_SDE_UIDLE_REV_102(uidle_cfg->uidle_rev)) {
+			set_bit(SDE_UIDLE_QACTIVE_OVERRIDE,
+					&uidle_cfg->features);
+			uidle_cfg->fal10_threshold =
+				SDE_UIDLE_FAL10_THRESHOLD_90;
+			uidle_cfg->max_fps = SDE_UIDLE_MAX_FPS_90;
+			uidle_cfg->max_fal1_fps = SDE_UIDLE_MAX_FPS_240;
 		}
 	} else {
 		pr_err("invalid uidle rev:0x%x, disabling uidle\n",
@@ -5114,7 +5124,7 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
 		set_bit(SDE_MDP_DHDR_MEMPOOL_4K, &sde_cfg->mdp[0].features);
 		sde_cfg->has_vig_p010 = true;
 		sde_cfg->true_inline_rot_rev = SDE_INLINE_ROT_VERSION_2_0_0;
-		sde_cfg->uidle_cfg.uidle_rev = SDE_UIDLE_VERSION_1_0_1;
+		sde_cfg->uidle_cfg.uidle_rev = SDE_UIDLE_VERSION_1_0_2;
 		sde_cfg->vbif_disable_inner_outer_shareable = true;
 		sde_cfg->dither_luma_mode_support = true;
 		sde_cfg->mdss_hw_block_size = 0x158;

msm/sde/sde_hw_catalog.h

@@ -125,11 +125,14 @@
  */
 #define SDE_UIDLE_VERSION_1_0_0		0x100
 #define SDE_UIDLE_VERSION_1_0_1		0x101
+#define SDE_UIDLE_VERSION_1_0_2		0x102
 
 #define IS_SDE_UIDLE_REV_100(rev) \
 	((rev) == SDE_UIDLE_VERSION_1_0_0)
 #define IS_SDE_UIDLE_REV_101(rev) \
 	((rev) == SDE_UIDLE_VERSION_1_0_1)
+#define IS_SDE_UIDLE_REV_102(rev) \
+	((rev) == SDE_UIDLE_VERSION_1_0_2)
 
 #define SDE_UIDLE_MAJOR(rev)		((rev) >> 8)
 
@@ -968,6 +971,7 @@ struct sde_mdp_cfg {
  *	                    This ratio is multiplied x1000 to allow
  *	                    3 decimal precision digits.
  * @max_fps:                maximum fps to allow micro idle
+ * @max_fal1_fps:           maximum fps to allow micro idle FAL1 only
  * @uidle_rev:              uidle revision supported by the target,
  *                          zero if no support
  * @debugfs_perf:           enable/disable performance counters and status
@@ -987,6 +991,7 @@ struct sde_uidle_cfg {
 	u32 fal10_threshold;
 	u32 max_dwnscale;
 	u32 max_fps;
+	u32 max_fal1_fps;
 	u32 uidle_rev;
 	u32 debugfs_perf;
 	bool debugfs_ctrl;

msm/sde/sde_hw_uidle.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  *
  */
 
@@ -161,10 +161,17 @@ void sde_hw_uidle_setup_ctl(struct sde_hw_uidle *uidle,
 		struct sde_uidle_ctl_cfg *cfg)
 {
 	struct sde_hw_blk_reg_map *c = &uidle->hw;
+	bool enable = false;
 	u32 reg_val;
 
 	reg_val = SDE_REG_READ(c, UIDLE_CTL);
-	reg_val = (reg_val & ~BIT(31)) | (cfg->uidle_enable ? BIT(31) : 0);
+
+	enable = (cfg->uidle_state > UIDLE_STATE_DISABLE &&
+		cfg->uidle_state < UIDLE_STATE_ENABLE_MAX);
+	reg_val = (reg_val & ~BIT(31)) | (enable ? BIT(31) : 0);
+	reg_val = (reg_val & ~BIT(30)) | (cfg->uidle_state
+			== UIDLE_STATE_FAL1_ONLY ? BIT(30) : 0);
+
 	reg_val = (reg_val & ~FAL10_DANGER_MSK) |
 		((cfg->fal10_danger << FAL10_DANGER_SHFT) &
 		FAL10_DANGER_MSK);

msm/sde/sde_hw_uidle.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
- * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
  *
  */
 
@@ -25,11 +25,18 @@ struct sde_hw_uidle;
 #define SDE_UIDLE_WD_HEART_BEAT 0
 #define SDE_UIDLE_WD_LOAD_VAL 18
 
+enum sde_uidle_state {
+	UIDLE_STATE_DISABLE = 0,
+	UIDLE_STATE_FAL1_ONLY,
+	UIDLE_STATE_FAL1_FAL10,
+	UIDLE_STATE_ENABLE_MAX,
+};
+
 struct sde_uidle_ctl_cfg {
 	u32 fal10_exit_cnt;
 	u32 fal10_exit_danger;
 	u32 fal10_danger;
-	bool uidle_enable;
+	enum sde_uidle_state uidle_state;
 };
 
 struct sde_uidle_wd_cfg {