Trigger callback to ISP each time when there is a change
in phy clock so that csid and tfe clock rate can be
updated accordingly. The argument passed in callback api is
the final phy clock rate that is applied.
CRs-Fixed: 2854066
Change-Id: Ia74465e4082e08b4c50338e0eb779f996afa2795
Signed-off-by: shiwgupt <quic_shiwgupt@quicinc.com>
Signed-off-by: shaduls <quic_shaduls@quicinc.com>
(cherry picked from commit 1fd5054f530a16a5bf90901ba4c8bf2025e136dc)
Dumping both ipe and bps clocks in case of frame process
failure. Added generic utility function to dump any hw's
clocks.
CRs-Fixed: 3297488
Change-Id: Ia952696b0288361bffaeadfd53041c72fd21f96d
Signed-off-by: Yash Upadhyay <quic_yupadhya@quicinc.com>
Signed-off-by: Alok Chauhan <quic_alokc@quicinc.com>
On current scheme, we put validation inside IO function, it's hard
to block subsequent accessing when facing invalid address and may
increase the number of cycles to do the register accessing as well.
This change limits the validation to only for the reg dump, we can
take following up operations when accessing wrong address for read
rather than printing uncertain logs.
CRs-Fixed: 3589725
Change-Id: I7d38a3ddb6c3f8e2915070f3c24629754abf76d7
Signed-off-by: Stark Lin <quic_starlin@quicinc.com>
(cherry picked from commit 159f8889a51178a92186e66e24e39bfdb01e87ee)
Kernel panic might be caused by improper register offset which
is not memory aligned during write or read operation, this change
adds a validation for the offset to avoid accessing invalid address.
CRs-Fixed: 3542219
Change-Id: I8761c8d416890bd4571be8a64118036c0173d303
Signed-off-by: Stark Lin <quic_starlin@quicinc.com>
Currently, lowest clk voting level supported is LowSVS, this
change will add support to a lower voting level, LowSVS_D1.
CRs-Fixed: 3480799
Change-Id: Ibdfe9d1d05aa45439a537cebe828cceea83f39d4
Signed-off-by: Atiya Kailany <quic_akailany@quicinc.com>
This change will allow clients voting through mmrm to use the new mmrm
api and vote according to their drv_type. This change affects
registering, unregistering and setting the clk rate to sw and
hw clients.
CRs-Fixed: 3385745
Change-Id: I11f76a0de3ba0d8d969093725d4c528afef51373
Signed-off-by: Atiya Kailany <quic_akailany@quicinc.com>
Sometimes need to avoid access clock/regulator/icc api, this change
add support bypass clock/regulator/icc wrapper through enable
some debugfs parameters and devicetree.
CRs-Fixed: 3445248
Change-Id: I0546975bf063625b39b771c776813e7dbff84e06
Signed-off-by: zhuo <quic_zhuo@quicinc.com>
Currently the maximum length of tag is 64, but in some
cases, the tag length we need is lager than 64, in
this case some information will be lost, which leads
to the failure to properly parse out the required
information. We need to make sure that all the tags
are the same length so that the parsing script can
parse them correctly. We also need to make sure that
the last character in tag is ":" in order for the
parsing script to get the full tag string correctly.
CRs-Fixed: 3467258
Change-Id: Ie8107ffd902d70d88026632a2c9fadaca0c276d8
Signed-off-by: mingpan <quic_mingpan@quicinc.com>
Update SOC util to be able to parse multiple irq names from DT and,
request, enable, disable multiple irq lines per soc.
All IRQ lines per SOC will have the same handler but different data,
so ISR will have their own private data to differentiate source of irq
in the same handling function.
CRs-Fixed: 3395596
Change-Id: Id9ca1cd3ef105d732a82decd7c8078bd29668326
Signed-off-by: Sokchetra Eung <quic_eung@quicinc.com>
On chipsets having cesta hw block support, for cesta supported clks
clk frequency can be changed during veritcal blanking based on
CSID DRV events. For this to happen, camera clients need to setup
high and low clock votes through hw clients. Use corresponding clk,
crm APIs to setup high, low clk frquencies and do channel switch
to apply newly set rates. Clients can also set clk frequency through
sw client which will set the floor. This feature helps in saving
power for usecases where vertical blanking is high such as
Fast Shutter usecase.
CRs-Fixed: 3294948
Change-Id: I1bcf650b439991a23b2a0f0f9a5162bdcd60dc64
Signed-off-by: Mukund Madhusudan Atre <quic_matre@quicinc.com>
Signed-off-by: Pavan Kumar Chilamkurthi <quic_pchilamk@quicinc.com>
This change is needed for domain id feature support.
When a PHY and its lanes for a particular CSID are
protected in a secure session, the same for other
unused CSIDs are to be protected as well. This is
to prevent other CSIDs from tapping the data streaming
onto those lanes if they share the same PHY.
For this, the clocks for other CSIDs (eg CSID-Lite)
need to be turned on. Given that the existing driver
turns on the clocks for the CSID in use, and that
this clock information is embedded within the CSID
hw blocks, these clocks are now exposed as optional
clocks to CPAS to enable the PHY driver to turn them
on during streamon for secure session.
CRs-Fixed: 3304650
Change-Id: I1415e78467208b6b4a74223521d964a199288857
Signed-off-by: Li Sha Lim <quic_lishlim@quicinc.com>
In function cam_ife_mgr_acquire_dev, will assign
cdm_reg_map to base_array according to index, but
the array length of base_array is less than
CAM_IFE_HW_NUM_MAX now, so it may cause to array
index out of bounds. If we acquire 8 IFEs, we
need to send cdm the reg_base for all 8.
CRs-Fixed: 3250612
Change-Id: I791659e1ad72d301de89fb374d37720ce58f102b
Signed-off-by: mingpan <quic_mingpan@quicinc.com>
Signed-off-by: Depeng Shao <quic_depengs@quicinc.com>
For some chipsets, qchannel handshake needs icp clk to be
enabled. Add support to enable icp clk while qchannel
handshake by adding as optional clk in cpas node. Whether
to enable icp clk or not is controlled through workaround
list populated for each chipset.
Add mechanism to retry qchannel acceptance if the first
auto try has failed, by explicity writing 0x1 to qchannel
ctrl register. This will bring back qchannel to good state.
CRs-Fixed: 3131613
Change-Id: Ie39a9789b2eb1bf9c0f6adb26fe6d6e1823eff70
Signed-off-by: Pavan Kumar Chilamkurthi <quic_pchilamk@quicinc.com>
Currently pinctrl state update operation is integrated
with platform resource operation. This can create unwanted
transition of pinctrl which can stay in suspend state.
This change detach and separate out the pinctrl entries
with index passed from devicetree. Pinctrl select
state operation is detach from platform enable/disable
operation to operate from device directly only for better
control with respect to operation.
CRs-Fixed: 2907475, 2954556
Change-Id: I918568f96e8888df6882f165458f5c4ab32d6348
Signed-off-by: Jigarkumar Zala <jzala@codeaurora.org>
Use mmrm interface to set clock rate on all
camera clks.
CRs-Fixed: 2901925
Change-Id: I2e4c31a11e0e068693ac15356e3b3dafcfa0b078
Signed-off-by: Pavan Kumar Chilamkurthi <pchilamk@codeaurora.org>
Source clocks that are shared with multiple devices need
to be consolidated before setting clock rate on them.
If not, a set call with lower freq from one device
overwrites the frequency that previously set by another
device, causing issues. Clk wrapper helps to consolidate
the frequency among multiple devices and set the max
frequency required by all of them. A shared clock notation
is defined in DT and go through clk wrapper based on that.
CRs-Fixed: 2901925
Change-Id: Ia5b2b5fd3c0619c994e27d96fad6e11d126de182
Signed-off-by: Pavan Kumar Chilamkurthi <pchilamk@codeaurora.org>
Clients like cpas scale some clocks like slow_ahb, fast_ahb
through vote level based on other hw's src clk freq while
the actual src clock (camnoc) is calculated and set directly
through set_src_clk API. This will overwrite freq of camnoc_axi
with the same level as AHB when ahb clocks are set. Do not
set src clk rate while setting rate for other clocks using level.
CRs-Fixed: 2793673
Change-Id: I5538a5cebf4e47c407a2bf9778136500b1162b4a
Signed-off-by: Pavan Kumar Chilamkurthi <pchilamk@codeaurora.org>
Enhance cpas state dump to get more information about
bandwidth and clock status. This additional state dump
can be enabled using debugfs.
adb shell "echo 1 > /sys/kernel/debug/camera_cpas/full_state_dump"
Traverse through all bw tree nodes and print info in each node.
Print current clk frequencies of all clocks that cpas enables.
Read rpmh bcm status registers to understand mmnoc clk freq.
Add cpas monitor to save important info whenever clients
notify with an event. This monitor info is printed in cpas
state dump.
CRs-Fixed: 2754299
Change-Id: Ib9007091f7e34127f1ca92498e2537b2a06887cb
Signed-off-by: Pavan Kumar Chilamkurthi <pchilamk@codeaurora.org>
msm: camera: tfe: Fix variable initialization issues
msm: camera: isp: Dual tfe event check with proper hw idx
msm: camera: smmu: Add support for non-contiguous mermory region
msm: camera: smmu: Use iommu best match algo for camera
msm: camera: ope: Optimize allocation of IO configuration
msm: camera: ope: Fix for KW Issues
msm: camera: ope: Add support for stripe level height configuration
msm: camera: tfe: Enable the delay line clc
msm: camera: ope: Fix false alarm for OPE HW timeout
msm: camera: tfe: Support register dump per request
msm: camera: ope: Increase max number of stripes
msm: camera: ope: Change packer and unpacker format in case NV12
msm: camera: tfe: Add packet code get command for tfe
msm: camera: ope: Trigger recovery in case of violation on write bus
msm: camera: ope: Protect ope hw reset with mutex
msm: camera: ope: Add a check for valid request in cdm callback
msm: camera: ope: Remove the BW & clock vote in release context
msm: camera: ope: Reduce OPE BUS memory
msm: camera: ope: Fix return value for ope acquire
msm: camera: ope: Fix false alarm for OPE request timeout
msm: camera: ope: Avoid deadlock during recovery after HW hang
msm: camera: tfe: tfe debug enhancement
msm: camera: cdm: Fix irq_data value in case of inline irq
msm: camera: flash: Switch off flash on provider crash
msm: camera: ope: Initialize ope hw mutex structure
msm: camera: cdm: Flush all available FIFOs during reset
msm: camera: cpas: Add mandatory bw option for axi ports clocks
msm: camera: ope: Use vzalloc to allocate the write bus ctx structure
msm: camera: ope: Fix handling of init hw failure
msm: camera: tfe: Enable per frame register dump for rdi only context
msm: camera: cdm: Protect cdm core status bits with mutex
msm: camera: cdm: correct the error check in cmd submit irq
msm: camera: ope: Fix unclock access during HW reset
msm: camera: ope: Program frame level settings after idle event
msm: camera: ope: Delay releasing of resources for last context
msm: camera: isp: Increase default SOF freeze timeout
msm: camera: smmu: Add map and unmap monitor
msm: camera: isp: Add trace events across ISP
msm: camera: smmu: Profile time taken for map, unmap
msm: camera: ope: Start context timer on receiving new request
msm: camera: tfe: Reduce stack size during set axi bw
msm: camera: cdm: Check for HW state before dumping registers
msm: camera: ope: Reduce stack footprint during acquire
msm: camera: tfe: Disable clock if tfe2 is not supported
msm: camera: cdm: Avoid cdm pause incase of BL submit
msm: camera: tfe: Optimize CSID IRQ logging
msm: camera: ope: Move request id validity check outside of lock
msm: camera: tfe: Correct the tfe hw manager dump logic
msm: camera: ope: Synchronize flush and submit BLs
msm: camera: cdm: Protect cdm reset status
msm: camera: cdm: Handle cdm deinit sequence properly
msm: camera: tfe: Reduce reset timeout to 100ms
msm: camera: ope: Fix hang detection
msm: camera: ope: Make non-fatal logs as debug and info logs
msm: camera: tfe: set overflow pending bit to zero after HW reset
msm: camera: ope: Do not disable CDM during error handling
msm: camera: ope: Add support for OPE Replay
msm: camera: ope: Stop OPE in case of init failure
msm: camera: ope: Synchronize process cmd and flush request
msm: camera: cdm: Fix CDM IRQ handling
msm: camera: tfe: LDAR dump for TFE
msm: camera: ope: Fix the length check for debug buffer
msm: camera: cdm: Fix CDM reset logic
msm: camera: ope: Dump debug registers in case of HW hang
msm: camera: tfe: Support the RDI bus port for line based mode
msm: camera: cdm: Handle out of order reset done events
msm: camera: ope: Consider other contexts during timeout
msm: camera: ope: Put GenIRQ in last stripe BL
msm: camera: tfe: Process the rdi interrupts for rdi only resource
msm: camera: jpeg: Check the HW state before accessing register
msm: camera: csiphy: Update csiphy power-up sequence for lito v2
msm: camera: cdm: Secure freeing of request lists using locks
msm: camera: cpas: Add support for Scuba camnoc
msm: camera: csiphy: Clear secure phy flags on release
msm: camera: tfe: validate the tfe bw num paths
msm: camera: ope: Reorder the reset order in ope acquire
msm: camera: ope: Dump debug registers in case of reset failure
msm: camera: ope: Add logic to detect hang in CDM
msm: camera: isp: Increase max count of cfg to support more init packets
msm: camera: core: Fix cpas axi clk rate overflow.
CRs-Fixed: 2668666
Change-Id: I882ca4bd117bebc7d1c62bc82299d69d7b5c9388
Signed-off-by: Trishansh Bhardwaj <tbhardwa@codeaurora.org>
When user space detects an error or does not receive
response for a request, Lets do a reset(LDAR) is triggered.
Before LDAR, user space sends flush command to the
kernel space.
In order to debug the cause for this situation and to dump
the information, user space sends a dump command to
kernel space before sending flush.
As a part of this command, it passes the culprit request id
and the buffer into which the information can be dumped.
Kernel space traverses across the drivers and find the culprit hw
and dumps the relevant information in the buffer.
This data is written to a file for offline processing.
This commit dumps the IFE, CSID registers, LUT tables and context
information, cmd buffers, timestamps information for
submit, apply, RUP, epoch and buffdones of the last 20
requests.
CRs-Fixed: 2612116
Change-Id: If83db59458c1e5ad778f3fa90cbc730122491c54
Signed-off-by: Gaurav Jindal <gjindal@codeaurora.org>
Different CDM hardware have different capability and registers.
With old register space, handling new features and operations
would have been a complex task. This change takes care of old
version of CDM and also changes the regspace to provide every
register's access to CDM.
This change further adds support for "arbitration" in case of
multi-context CDMs.
Exports reset functionality to clients, detection of CDM hang.
Flushing the CDM requests and dumping the FIFO content for all
contexts.
It also adds submitting "debug_gen_irq" as BL_done IRQ is only
an indication for availability of FIFO's. The AHB operations
are completed can only be known if the added "debug_gen_irqs"
gets executed and are received by the CDM.
CRs-Fixed: 2594541
Change-Id: I9846b1c5320ba652c5d3b7d83d616d2dabc843e1
Signed-off-by: Abhilash Kumar <krabhi@codeaurora.org>
Signed-off-by: Trishansh Bhardwaj <tbhardwa@codeaurora.org>
Currently image sensor need single source of the regulator per
category. Some sensor needs extra analog voltage for the functionality,
which require to draw power from multiple voltage regulator sources.
This change extends supports to add multiple voltage sources for
analog voltage.
CRs-Fixed: 2584631
Change-Id: I2d76cfb0fb971758c0d596ffd543aa3926a8886d
Signed-off-by: Jigarkumar Zala <jzala@codeaurora.org>
Adds fixes to makefile in order to support legacy kernel build systems.
CRs-Fixed: 2560543
Change-Id: Iab571871e5171aab501c41496cc09e3c5d942985
Signed-off-by: Karthik Jayakumar <kjayakum@codeaurora.org>
Removed unused functions that called clk_set_flag, which has been
deprecated in linux kernel 5.x.
CRs-Fixed: 2554484
Change-Id: I0062383b0b059e6b359229f4b33470713289abb4
Signed-off-by: Karthik Jayakumar <kjayakum@codeaurora.org>
Certain register values are required by user space during flush
to apply settings accordingly. Also, support for dumping registers
at the time of error is needed for debugging. Add support for
dumping register values in a range of offsets to given cmd buffer.
Change-Id: I5912118809f7a7dd701a555639d1057ffe665ce1
Signed-off-by: Mukund Madhusudan Atre <matre@codeaurora.org>
This change updates the scalable clock based on
hw src clock. Also, removed cam_soc_util_get_vote_level()
as it is duplicating the functionality with
cam_soc_util_get_clk_level() api.
Change-Id: I001264d150849770ef664ecc206a66f8a4f54412
Signed-off-by: Jigarkumar Zala <jzala@codeaurora.org>
Bring over camera driver changes as of msm-4.19
commit 5a5551a7 (Merge "msm: camera: reqmgr: Fix CRM
shift one req issue").
Change-Id: Ic0c2b2d74d1b3470c1c51d98228e312fb13c501a
Signed-off-by: Jigarkumar Zala <jzala@codeaurora.org>
