05349feaa2
Bring over camera driver changes as of msm-4.19 commit 5a5551a7 (Merge "msm: camera: reqmgr: Fix CRM shift one req issue"). Change-Id: Ic0c2b2d74d1b3470c1c51d98228e312fb13c501a Signed-off-by: Jigarkumar Zala <jzala@codeaurora.org>
639 lines
22 KiB
C
639 lines
22 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
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*/
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#ifndef _CAM_SOC_UTIL_H_
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#define _CAM_SOC_UTIL_H_
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/platform_device.h>
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#include <linux/i2c.h>
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#include <linux/regulator/consumer.h>
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#include <linux/debugfs.h>
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#include <linux/of_fdt.h>
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#include "cam_io_util.h"
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#define NO_SET_RATE -1
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#define INIT_RATE -2
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/* maximum number of device block */
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#define CAM_SOC_MAX_BLOCK 7
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/* maximum number of device base */
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#define CAM_SOC_MAX_BASE CAM_SOC_MAX_BLOCK
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/* maximum number of device regulator */
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#define CAM_SOC_MAX_REGULATOR 5
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/* maximum number of device clock */
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#define CAM_SOC_MAX_CLK 32
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/* DDR device types */
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#define DDR_TYPE_LPDDR4 6
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#define DDR_TYPE_LPDDR4X 7
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#define DDR_TYPE_LPDDR5 8
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#define DDR_TYPE_LPDDR5X 9
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/**
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* enum cam_vote_level - Enum for voting level
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*
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* @CAM_SUSPEND_VOTE : Suspend vote
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* @CAM_MINSVS_VOTE : Min SVS vote
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* @CAM_LOWSVS_VOTE : Low SVS vote
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* @CAM_SVS_VOTE : SVS vote
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* @CAM_SVSL1_VOTE : SVS Plus vote
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* @CAM_NOMINAL_VOTE : Nominal vote
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* @CAM_NOMINALL1_VOTE: Nominal plus vote
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* @CAM_TURBO_VOTE : Turbo vote
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* @CAM_MAX_VOTE : Max voting level, This is invalid level.
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*/
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enum cam_vote_level {
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CAM_SUSPEND_VOTE,
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CAM_MINSVS_VOTE,
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CAM_LOWSVS_VOTE,
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CAM_SVS_VOTE,
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CAM_SVSL1_VOTE,
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CAM_NOMINAL_VOTE,
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CAM_NOMINALL1_VOTE,
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CAM_TURBO_VOTE,
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CAM_MAX_VOTE,
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};
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/* pinctrl states */
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#define CAM_SOC_PINCTRL_STATE_SLEEP "cam_suspend"
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#define CAM_SOC_PINCTRL_STATE_DEFAULT "cam_default"
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/**
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* struct cam_soc_reg_map: Information about the mapped register space
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*
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* @mem_base: Starting location of MAPPED register space
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* @mem_cam_base: Starting offset of this register space compared
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* to ENTIRE Camera register space
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* @size: Size of register space
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**/
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struct cam_soc_reg_map {
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void __iomem *mem_base;
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uint32_t mem_cam_base;
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resource_size_t size;
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};
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/**
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* struct cam_soc_pinctrl_info: Information about pinctrl data
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*
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* @pinctrl: pintrl object
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* @gpio_state_active: default pinctrl state
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* @gpio_state_suspend suspend state of pinctrl
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**/
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struct cam_soc_pinctrl_info {
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struct pinctrl *pinctrl;
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struct pinctrl_state *gpio_state_active;
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struct pinctrl_state *gpio_state_suspend;
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};
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/**
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* struct cam_soc_gpio_data: Information about the gpio pins
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*
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* @cam_gpio_common_tbl: It is list of al the gpios present in gpios node
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* @cam_gpio_common_tbl_size: It is equal to number of gpios prsent in
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* gpios node in DTSI
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* @cam_gpio_req_tbl It is list of al the requesetd gpios
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* @cam_gpio_req_tbl_size: It is size of requested gpios
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**/
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struct cam_soc_gpio_data {
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struct gpio *cam_gpio_common_tbl;
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uint8_t cam_gpio_common_tbl_size;
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struct gpio *cam_gpio_req_tbl;
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uint8_t cam_gpio_req_tbl_size;
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};
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/**
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* struct cam_hw_soc_info: Soc information pertaining to specific instance of
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* Camera hardware driver module
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*
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* @pdev: Platform device pointer
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* @device: Device pointer
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* @hw_version: Camera device version
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* @index: Instance id for the camera device
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* @dev_name: Device Name
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* @irq_name: Name of the irq associated with the device
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* @irq_line: Irq resource
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* @irq_data: Private data that is passed when IRQ is requested
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* @compatible: Compatible string associated with the device
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* @num_mem_block: Number of entry in the "reg-names"
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* @mem_block_name: Array of the reg block name
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* @mem_block_cam_base: Array of offset of this register space compared
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* to ENTIRE Camera register space
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* @mem_block: Associated resource structs
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* @reg_map: Array of Mapped register info for the "reg-names"
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* @num_reg_map: Number of mapped register space associated
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* with mem_block. num_reg_map = num_mem_block in
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* most cases
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* @reserve_mem: Whether to reserve memory for Mem blocks
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* @num_rgltr: Number of regulators
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* @rgltr_name: Array of regulator names
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* @rgltr_ctrl_support: Whether regulator control is supported
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* @rgltr_min_volt: Array of minimum regulator voltage
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* @rgltr_max_volt: Array of maximum regulator voltage
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* @rgltr_op_mode: Array of regulator operation mode
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* @rgltr_type: Array of regulator names
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* @rgltr: Array of associated regulator resources
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* @rgltr_delay: Array of regulator delay values
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* @num_clk: Number of clocks
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* @clk_name: Array of clock names
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* @clk: Array of associated clock resources
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* @clk_rate: 2D array of clock rates representing clock rate
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* values at different vote levels
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* @prev_clk_level Last vote level
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* @src_clk_idx: Source clock index that is rate-controllable
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* @clk_level_valid: Indicates whether corresponding level is valid
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* @gpio_data: Pointer to gpio info
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* @pinctrl_info: Pointer to pinctrl info
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* @dentry: Debugfs entry
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* @clk_level_override: Clk level set from debugfs
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* @clk_control: Enable/disable clk rate control through debugfs
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* @cam_cx_ipeak_enable cx-ipeak enable/disable flag
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* @cam_cx_ipeak_bit cx-ipeak mask for driver
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* @soc_private: Soc private data
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*/
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struct cam_hw_soc_info {
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struct platform_device *pdev;
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struct device *dev;
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uint32_t hw_version;
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uint32_t index;
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const char *dev_name;
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const char *irq_name;
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struct resource *irq_line;
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void *irq_data;
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const char *compatible;
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uint32_t num_mem_block;
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const char *mem_block_name[CAM_SOC_MAX_BLOCK];
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uint32_t mem_block_cam_base[CAM_SOC_MAX_BLOCK];
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struct resource *mem_block[CAM_SOC_MAX_BLOCK];
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struct cam_soc_reg_map reg_map[CAM_SOC_MAX_BASE];
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uint32_t num_reg_map;
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uint32_t reserve_mem;
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uint32_t num_rgltr;
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const char *rgltr_name[CAM_SOC_MAX_REGULATOR];
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uint32_t rgltr_ctrl_support;
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uint32_t rgltr_min_volt[CAM_SOC_MAX_REGULATOR];
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uint32_t rgltr_max_volt[CAM_SOC_MAX_REGULATOR];
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uint32_t rgltr_op_mode[CAM_SOC_MAX_REGULATOR];
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uint32_t rgltr_type[CAM_SOC_MAX_REGULATOR];
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struct regulator *rgltr[CAM_SOC_MAX_REGULATOR];
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uint32_t rgltr_delay[CAM_SOC_MAX_REGULATOR];
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uint32_t use_shared_clk;
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uint32_t num_clk;
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const char *clk_name[CAM_SOC_MAX_CLK];
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struct clk *clk[CAM_SOC_MAX_CLK];
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int32_t clk_rate[CAM_MAX_VOTE][CAM_SOC_MAX_CLK];
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int32_t prev_clk_level;
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int32_t src_clk_idx;
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bool clk_level_valid[CAM_MAX_VOTE];
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struct cam_soc_gpio_data *gpio_data;
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struct cam_soc_pinctrl_info pinctrl_info;
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struct dentry *dentry;
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uint32_t clk_level_override;
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bool clk_control_enable;
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bool cam_cx_ipeak_enable;
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int32_t cam_cx_ipeak_bit;
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void *soc_private;
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};
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/*
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* CAM_SOC_GET_REG_MAP_START
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*
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* @brief: This MACRO will get the mapped starting address
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* where the register space can be accessed
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*
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* @__soc_info: Device soc information
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* @__base_index: Index of register space in the HW block
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*
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* @return: Returns a pointer to the mapped register memory
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*/
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#define CAM_SOC_GET_REG_MAP_START(__soc_info, __base_index) \
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((!__soc_info || __base_index >= __soc_info->num_reg_map) ? \
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NULL : __soc_info->reg_map[__base_index].mem_base)
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/*
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* CAM_SOC_GET_REG_MAP_CAM_BASE
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*
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* @brief: This MACRO will get the cam_base of the
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* register space
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*
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* @__soc_info: Device soc information
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* @__base_index: Index of register space in the HW block
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*
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* @return: Returns an int32_t value.
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* Failure: -1
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* Success: Starting offset of register space compared
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* to entire Camera Register Map
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*/
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#define CAM_SOC_GET_REG_MAP_CAM_BASE(__soc_info, __base_index) \
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((!__soc_info || __base_index >= __soc_info->num_reg_map) ? \
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-1 : __soc_info->reg_map[__base_index].mem_cam_base)
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/*
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* CAM_SOC_GET_REG_MAP_SIZE
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*
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* @brief: This MACRO will get the size of the mapped
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* register space
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*
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* @__soc_info: Device soc information
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* @__base_index: Index of register space in the HW block
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*
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* @return: Returns a uint32_t value.
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* Failure: 0
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* Success: Non-zero size of mapped register space
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*/
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#define CAM_SOC_GET_REG_MAP_SIZE(__soc_info, __base_index) \
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((!__soc_info || __base_index >= __soc_info->num_reg_map) ? \
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0 : __soc_info->reg_map[__base_index].size)
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/**
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* cam_soc_util_get_level_from_string()
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*
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* @brief: Get the associated vote level for the input string
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*
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* @string: Input string to compare with.
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* @level: Vote level corresponds to input string.
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*
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* @return: Success or failure
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*/
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int cam_soc_util_get_level_from_string(const char *string,
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enum cam_vote_level *level);
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/**
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* cam_soc_util_get_dt_properties()
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*
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* @brief: Parse the DT and populate the common properties that
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* are part of the soc_info structure - register map,
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* clocks, regulators, irq, etc.
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*
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* @soc_info: Device soc struct to be populated
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*
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* @return: Success or failure
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*/
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int cam_soc_util_get_dt_properties(struct cam_hw_soc_info *soc_info);
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/**
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* cam_soc_util_request_platform_resource()
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*
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* @brief: Request regulator, irq, and clock resources
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*
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* @soc_info: Device soc information
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* @handler: Irq handler function pointer
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* @irq_data: Irq handler function CB data
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*
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* @return: Success or failure
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*/
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int cam_soc_util_request_platform_resource(struct cam_hw_soc_info *soc_info,
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irq_handler_t handler, void *irq_data);
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/**
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* cam_soc_util_release_platform_resource()
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*
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* @brief: Release regulator, irq, and clock resources
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*
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* @soc_info: Device soc information
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*
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* @return: Success or failure
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*/
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int cam_soc_util_release_platform_resource(struct cam_hw_soc_info *soc_info);
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/**
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* cam_soc_util_enable_platform_resource()
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*
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* @brief: Enable regulator, irq resources
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*
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* @soc_info: Device soc information
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* @enable_clocks: Boolean flag:
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* TRUE: Enable all clocks in soc_info Now.
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* False: Don't enable clocks Now. Driver will
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* enable independently.
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* @clk_level: Clock level to be applied.
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* Applicable only if enable_clocks is true
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* Valid range : 0 to (CAM_MAX_VOTE - 1)
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* @enable_irq: Boolean flag:
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* TRUE: Enable IRQ in soc_info Now.
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* False: Don't enable IRQ Now. Driver will
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* enable independently.
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*
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* @return: Success or failure
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*/
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int cam_soc_util_enable_platform_resource(struct cam_hw_soc_info *soc_info,
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bool enable_clocks, enum cam_vote_level clk_level, bool enable_irq);
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/**
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* cam_soc_util_disable_platform_resource()
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*
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* @brief: Disable regulator, irq resources
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*
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* @soc_info: Device soc information
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* @disable_irq: Boolean flag:
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* TRUE: Disable IRQ in soc_info Now.
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* False: Don't disable IRQ Now. Driver will
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* disable independently.
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*
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* @return: Success or failure
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*/
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int cam_soc_util_disable_platform_resource(struct cam_hw_soc_info *soc_info,
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bool disable_clocks, bool disable_irq);
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/**
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* cam_soc_util_get_clk_round_rate()
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*
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* @brief: Get the rounded clock rate for the given clock's
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* clock rate value
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*
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* @soc_info: Device soc information
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* @clk_index: Clock index in soc_info for which round rate is needed
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* @clk_rate: Input clock rate for which rounded rate is needed
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*
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* @return: Rounded clock rate
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*/
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long cam_soc_util_get_clk_round_rate(struct cam_hw_soc_info *soc_info,
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uint32_t clk_index, unsigned long clk_rate);
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/**
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* cam_soc_util_set_clk_flags()
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*
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* @brief: Camera SOC util to set the flags for a specified clock
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*
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* @soc_info: Device soc information
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* @clk_index: Clock index in soc_info for which flags are to be set
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* @flags: Flags to set
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*
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* @return: Success or Failure
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*/
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int cam_soc_util_set_clk_flags(struct cam_hw_soc_info *soc_info,
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uint32_t clk_index, unsigned long flags);
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/**
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* cam_soc_util_set_src_clk_rate()
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*
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* @brief: Set the rate on the source clock.
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*
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* @soc_info: Device soc information
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* @clk_rate: Clock rate associated with the src clk
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*
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* @return: success or failure
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*/
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int cam_soc_util_set_src_clk_rate(struct cam_hw_soc_info *soc_info,
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int32_t clk_rate);
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/**
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* cam_soc_util_get_option_clk_by_name()
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*
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* @brief: Get reference to optional clk using name
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*
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* @soc_info: Device soc information
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* @clk_name: Name of clock to find reference for
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* @clk: Clock reference pointer to be filled if Success
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* @clk_index: Clk index in the option clk array to be returned
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* @clk_rate: Clk rate in the option clk array
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*
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* @return: 0: Success
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* Negative: Failure
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*/
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int cam_soc_util_get_option_clk_by_name(struct cam_hw_soc_info *soc_info,
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const char *clk_name, struct clk **clk, int32_t *clk_index,
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int32_t *clk_rate);
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/**
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* cam_soc_util_clk_put()
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*
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* @brief: Put clock specified in params
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*
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* @clk: Reference to the Clock that needs to be put
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*
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* @return: Success or failure
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*/
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int cam_soc_util_clk_put(struct clk **clk);
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/**
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* cam_soc_util_clk_enable()
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*
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* @brief: Enable clock specified in params
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*
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* @clk: Clock that needs to be turned ON
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* @clk_name: Clocks name associated with clk
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* @clk_rate: Clocks rate associated with clk
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*
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* @return: Success or failure
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*/
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int cam_soc_util_clk_enable(struct clk *clk, const char *clk_name,
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int32_t clk_rate);
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/**
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* cam_soc_util_set_clk_rate_level()
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*
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* @brief: Apply clock rates for the requested level.
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* This applies the new requested level for all
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* the clocks listed in DT based on their values.
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*
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* @soc_info: Device soc information
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* @clk_level: Clock level number to set
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*
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* @return: Success or failure
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*/
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int cam_soc_util_set_clk_rate_level(struct cam_hw_soc_info *soc_info,
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enum cam_vote_level clk_level);
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/**
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* cam_soc_util_clk_disable()
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*
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* @brief: Disable clock specified in params
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*
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* @clk: Clock that needs to be turned OFF
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* @clk_name: Clocks name associated with clk
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*
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* @return: Success or failure
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*/
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int cam_soc_util_clk_disable(struct clk *clk, const char *clk_name);
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/**
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* cam_soc_util_irq_enable()
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*
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* @brief: Enable IRQ in SOC
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*
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* @soc_info: Device soc information
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*
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* @return: Success or failure
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*/
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int cam_soc_util_irq_enable(struct cam_hw_soc_info *soc_info);
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/**
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* cam_soc_util_irq_disable()
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*
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* @brief: Disable IRQ in SOC
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*
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* @soc_info: Device soc information
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*
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* @return: Success or failure
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*/
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int cam_soc_util_irq_disable(struct cam_hw_soc_info *soc_info);
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/**
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* cam_soc_util_regulator_enable()
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*
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* @brief: Enable single regulator
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*
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* @rgltr Regulator that needs to be turned ON
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* @rgltr_name Associated Regulator name
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* @rgltr_min_volt: Requested minimum volatage
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* @rgltr_max_volt: Requested maximum volatage
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* @rgltr_op_mode: Requested Load
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* @rgltr_delay: Requested delay needed aaftre enabling regulator
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*
|
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* @return: Success or failure
|
|
*/
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int cam_soc_util_regulator_enable(struct regulator *rgltr,
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const char *rgltr_name,
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uint32_t rgltr_min_volt, uint32_t rgltr_max_volt,
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uint32_t rgltr_op_mode, uint32_t rgltr_delay);
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/**
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* cam_soc_util_regulator_enable()
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*
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* @brief: Disable single regulator
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*
|
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* @rgltr Regulator that needs to be turned ON
|
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* @rgltr_name Associated Regulator name
|
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* @rgltr_min_volt: Requested minimum volatage
|
|
* @rgltr_max_volt: Requested maximum volatage
|
|
* @rgltr_op_mode: Requested Load
|
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* @rgltr_delay: Requested delay needed aaftre enabling regulator
|
|
*
|
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* @return: Success or failure
|
|
*/
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int cam_soc_util_regulator_disable(struct regulator *rgltr,
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const char *rgltr_name,
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uint32_t rgltr_min_volt, uint32_t rgltr_max_volt,
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uint32_t rgltr_op_mode, uint32_t rgltr_delay);
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|
|
|
|
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/**
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* cam_soc_util_w()
|
|
*
|
|
* @brief: Camera SOC util for register write
|
|
*
|
|
* @soc_info: Device soc information
|
|
* @base_index: Index of register space in the HW block
|
|
* @offset: Offset of register to be read
|
|
* @data: Value to be written
|
|
*
|
|
* @return: Success or Failure
|
|
*/
|
|
static inline int cam_soc_util_w(struct cam_hw_soc_info *soc_info,
|
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uint32_t base_index, uint32_t offset, uint32_t data)
|
|
{
|
|
if (!CAM_SOC_GET_REG_MAP_START(soc_info, base_index))
|
|
return -EINVAL;
|
|
return cam_io_w(data,
|
|
CAM_SOC_GET_REG_MAP_START(soc_info, base_index) + offset);
|
|
}
|
|
|
|
/**
|
|
* cam_soc_util_w_mb()
|
|
*
|
|
* @brief: Camera SOC util for register write with memory barrier.
|
|
* Memory Barrier is only before the write to ensure the
|
|
* order. If need to ensure this write is also flushed
|
|
* call wmb() independently in the caller.
|
|
*
|
|
* @soc_info: Device soc information
|
|
* @base_index: Index of register space in the HW block
|
|
* @offset: Offset of register to be read
|
|
* @data: Value to be written
|
|
*
|
|
* @return: Success or Failure
|
|
*/
|
|
static inline int cam_soc_util_w_mb(struct cam_hw_soc_info *soc_info,
|
|
uint32_t base_index, uint32_t offset, uint32_t data)
|
|
{
|
|
if (!CAM_SOC_GET_REG_MAP_START(soc_info, base_index))
|
|
return -EINVAL;
|
|
return cam_io_w_mb(data,
|
|
CAM_SOC_GET_REG_MAP_START(soc_info, base_index) + offset);
|
|
}
|
|
|
|
/**
|
|
* cam_soc_util_r()
|
|
*
|
|
* @brief: Camera SOC util for register read
|
|
*
|
|
* @soc_info: Device soc information
|
|
* @base_index: Index of register space in the HW block
|
|
* @offset: Offset of register to be read
|
|
*
|
|
* @return: Value read from the register address
|
|
*/
|
|
static inline uint32_t cam_soc_util_r(struct cam_hw_soc_info *soc_info,
|
|
uint32_t base_index, uint32_t offset)
|
|
{
|
|
if (!CAM_SOC_GET_REG_MAP_START(soc_info, base_index))
|
|
return 0;
|
|
return cam_io_r(
|
|
CAM_SOC_GET_REG_MAP_START(soc_info, base_index) + offset);
|
|
}
|
|
|
|
/**
|
|
* cam_soc_util_r_mb()
|
|
*
|
|
* @brief: Camera SOC util for register read with memory barrier.
|
|
* Memory Barrier is only before the write to ensure the
|
|
* order. If need to ensure this write is also flushed
|
|
* call rmb() independently in the caller.
|
|
*
|
|
* @soc_info: Device soc information
|
|
* @base_index: Index of register space in the HW block
|
|
* @offset: Offset of register to be read
|
|
*
|
|
* @return: Value read from the register address
|
|
*/
|
|
static inline uint32_t cam_soc_util_r_mb(struct cam_hw_soc_info *soc_info,
|
|
uint32_t base_index, uint32_t offset)
|
|
{
|
|
if (!CAM_SOC_GET_REG_MAP_START(soc_info, base_index))
|
|
return 0;
|
|
return cam_io_r_mb(
|
|
CAM_SOC_GET_REG_MAP_START(soc_info, base_index) + offset);
|
|
}
|
|
|
|
/**
|
|
* cam_soc_util_reg_dump()
|
|
*
|
|
* @brief: Camera SOC util for dumping a range of register
|
|
*
|
|
* @soc_info: Device soc information
|
|
* @base_index: Index of register space in the HW block
|
|
* @offset: Start register offset for the dump
|
|
* @size: Size specifying the range for dump
|
|
*
|
|
* @return: Success or Failure
|
|
*/
|
|
int cam_soc_util_reg_dump(struct cam_hw_soc_info *soc_info,
|
|
uint32_t base_index, uint32_t offset, int size);
|
|
|
|
void cam_soc_util_clk_disable_default(struct cam_hw_soc_info *soc_info);
|
|
|
|
int cam_soc_util_clk_enable_default(struct cam_hw_soc_info *soc_info,
|
|
enum cam_vote_level clk_level);
|
|
|
|
uint32_t cam_soc_util_get_vote_level(struct cam_hw_soc_info *soc_info,
|
|
uint64_t clock_rate);
|
|
|
|
#endif /* _CAM_SOC_UTIL_H_ */
|