The current scenario is as follows commit N with autorefresh
enabled and frame starts processing. On suspend commit N+1,
during virt_disable software resets CTL path after autorefresh
config is disabled. Since in hardware frame is still processing
sw reset is causing fifo underflow. This change waits for
vsync so that current autorefresh frame transaction completes
before issuing a CTL_SW_RESET.
Change-Id: Ib0662837e54b14cea6ab835a1093a2f048c473be
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
During qsync frequency step down, it is possible for the changing
frame window to lead to frame buffers being transferred when it
is unsafe to update. Pineapple r2 hardware supports using the
panel's TE level, instead of the start window, to trigger the
frame transfer.
This change enables using TE level during QSYNC or AVR, if the
hardware supports it.
Change-Id: Ie675edaaeb80921c639905395b709f4c67134fc7
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Modify the default INTF TE sync threshold config in cmd-mode to
32-bit max based on the INTF TE 32-bit support.
Change-Id: I963ffa8ae37bce0e85deb335609857c17e32d6b0
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Change adds support for storing the INTF watchdog timer long term jitter
curve state. The state before collapse is stored in wd_jitter and
restore back during power restore.
Change-Id: Id83b5cc754daea89d7844ab67b38e12199525ff8
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
This change adds support for INTF TE using 32 bit values and
single update per TE. These features help ensure that during
QSync mode the TE does not overrun in certain late trigger uses.
Change-Id: I893d0cde81320c3f17604694a4d8ee52b29a9425
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
When qsync is enabled with a large threshold start window, there
is a chance that two frames can be latched by mdp HW in single
vsync window. This change overrides the tearcheck rd_ptr_val
to a value larger than the end of the Tear check start window
to ensure new frame is not latched in current vsync window.
Change-Id: I21273f0bca83747210792b911e964dfd2d50079f
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
MDSS 9.0.0 added support for logging MDP_VSYNC timestamp. Use it for
video-mode panels and rely on PANEL_VSYNC timestamp for cmd-mode panels
as it relies on external panel TE.
Change-Id: I09b25d893075bee7cb2da98d4c4b4e54eb09bd6e
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
The sde_hw_blk was meant to be a generic base object for all
SDE HW blocks, however, it enforces using a common set of ops
which is not practical when blocks have different capabilities.
Since this object was never used as intended and is not doing
anything functional today, remove the dead weight.
Change-Id: If76006c1ae5c62e8d7d77b100837dbaf6c661bd3
Signed-off-by: Steve Cohen <quic_cohens@quicinc.com>
Add AVR step support so SW can trigger a late frame and instead
of immediately triggering, HW will perform the update at the
start of the next step interval. This allows for a fixed SW
vsync timeline to be maintained in userland, eliminating the
usual drift from the actual HW vsync caused by a late frame.
This change adds AVR_STEP support via a DRM property.
Change-Id: I4cf8a296989805f134c2165a3bed0b050bb09c96
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Report the AVR_STATUS which indicates if there's a pending
trigger when Adaptive Variable Refresh feature is enabled.
This allows SW to detect whether the old frame is repeated
or if the new frame was taken when the trigger is very
close to Vsync.
Change-Id: I6b04482e5c4c3bb92bad426c529c1fd3612d41c3
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
From MDSS 8.x, vsync timestamp counter register is added in all the
interfaces. Add interface to get the vsync counter and use the global
qtmr reference counter to get the counter delta. This can be used
with reference to the curret ktime to deduce the accurate vsync
timestamp. This utility is intended to be used for setting the vblank
and retire fence timestamps which would be notified to user-mode.
Change-Id: I608a284c035cda50053eedbb311f1f54b3d3d557
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
From MDSS 8.x INTF line/frame counters can be reset through
a register. Reset these counters during timing engine enable /
tear-check enable to keep track of meaningful counters, which
would be useful during debugging. Additionally, reset the
counters during cont-splash modeset to track the number of
auto-refresh frames while disabling it during the first frame.
Change-Id: I66b45f5b29793df1fb4635972b1c614ad8c3b5b3
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Watchdog timer is moving from TOP to INTF. This change adds
support for movement and ensures backwards compatibility.
Vsync select only needs to specify whether or not to use
Timer 0 associated with the interface. It does not need to
select between Timer 0-4.
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Change-Id: I9d89a8cb1ea607e9fc0bdbffa0a6a9acceff7f13
Add the INTF interrupt status register value to the underrun
line count event log to assist in debugging these issues.
Change-Id: I847cb12f8b4565d5f04667e0abda5d051a6194b2
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Fix prefill line calculation for high refresh rate
usecase and define correct number of prefill lines
for lahaina target.
Change-Id: Ib3467b9beb43de9c5faa2b1af2d8873a89c9c481
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
From Lahaina onwards, widebus is enabled for compressed DSI stream.
This change adjusts interface timing parameters to account for widebus.
Change-Id: Ie6b739ed2cdb515064e3a94404b3e0fe07755d7e
Signed-off-by: Rajkumar Subbiah <rsubbia@codeaurora.org>
Update autorefresh disable sequence-2 by avoiding
tearcheck enable configuration. Updated sequence
will trigger the frame by resetting the write
line count with tearcheck start position.
Change-Id: I984251c0cb23475f20cd5ea62122a167324d6670
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
This change adds logic to align timing engine vsync with panel
tear check if it is supported.
Change-Id: I3f881f392929589848c893f567822b21c0650000
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
Add underrun line count information for each underrun.
Change-Id: I34a740c33240fa8d444f4bbc3b8b014b0282fca1
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
This change enables the interface hw block to accept
64-bit compressed pixels. This configuration is enabled based
on hw capability. For current hw, this is required any time
the compressed pixels flow through the interface block,
whereas in the previous version of DPU hw this configuration
is only required for topology using 4 way dsc merge.
Change-Id: I7bf79d035dba5084c5057022a7fa1117479e8d52
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
This change ports the missing changes from 4.14 to 4.19
that were missed. It includes changes up until
commit 0f8fb25421ff ("cnss2: Add device version to
SOC info structure").
Change-Id: Idfdfe891f146e389e3c65cc3fc4c98d93220e789
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
This change brings msm display driver including sde,
dp, dsi, rotator, dsi pll and dp pll from base 4.19 kernel
project. It is first source code snapshot from base kernel project.
Change-Id: Iec864c064ce5ea04e170f24414c728684002f284
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
