If DSC 4hs merge is enabled and disabled on n+1 commit, possible
due to resolution switch, driver does not currently clear the
previous programming.
This change cleares dsc 4hs merge enable if it is not enabled.
Change-Id: I4024073362257b7efabcff22603bcb28a0bc4c5a
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
This feature enables using all available bits when ICH
error calculations are made. This improves precision and
image quality when there are more than 8 bits per component.
Change-Id: I851f05418283d0e731332d4069e3b6e57487b9a3
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
* quic/display-kernel.lnx.5.10:
disp: msm: sde: avoid error during fal10_veto override enablement
disp: msm: update copyright description
disp: msm: sde: configure dest_scaler op_mode for two independent displays
disp: msm: dp: updated copyright set for 4nm target
Revert "disp: msm: sde: consider max of actual and default prefill lines"
disp: msm: sde: Reset backlight scale when HWC is stopped
disp: msm: dp: avoid duplicate read of link status
disp: msm: dsi: update vreg_ctrl settings for cape
disp: msm: fail commit if drm_gem_obj was found attached to a sec CB
disp: msm: dp: updated register values for 4nm target
disp: msm: sde: update framedata event handling
disp: msm: dsi: Add new phy comaptible string for cape
disp: msm: sde: software override for fal10 in cwb enable
disp: msm: update cleanup during bind failure in msm_drm_component_init
disp: msm: sde: dump user input_fence info on spec fence timeout
disp: msm: sde: add null pointer check for encoder current master
disp: msm: dsi: enable DMA start window scheduling for broadcast commands
disp: msm: sde: avoid alignment checks for linear formats
disp: msm: reset thread priority work on every new run
disp: msm: sde: send power on event for cont. splash
disp: msm: sde: always set CTL_x_UIDLE_ACTIVE register to "1"
disp: msm: use vzalloc for large allocations
disp: msm: sde: Add support to limit DSC size to 10k
disp: msm: sde: add tx wait during DMS for sim panel
disp: msm: dsi: add check for any queued DSI CMDs before clock force update
disp: msm: sde: correct pp block allocation during dcwb dither programming
disp: msm: sde: avoid setting of max vblank count
disp: msm: sde: add cached lut flag in sde plane
disp: msm: sde: avoid use after free in msm_lastclose
disp: msm: sde: update TEAR_SYNC_WRCOUNT register before vsync counter
disp: msm: dsi: Support uncompressed rgb101010 format
disp: msm: sde: update idle_pc_enabled flag for all encoders
disp: msm: sde: flush esd work before disabling the encoder
disp: msm: sde: allow qsync update along with modeset
disp: msm: dp: avoid dp sw reset on disconnect path
disp: msm: sde: consider max of actual and default prefill lines
disp: msm: ensure vbif debugbus not in use is disabled
disp: msm: sde: update cached encoder mask if required
disp: msm: sde: while timing engine enabling poll for active region
disp: msm: enable cache flag for dumb buffer
disp: msm: sde: disable ot limit for cwb
disp: msm: sde: avoid race condition at vm release
disp: msm: dsi: set qsync min fps list length to zero
disp: msm: sde: reset mixers in crtc when ctl datapath switches
disp: msm: sde: update vm state atomic check for non-primary usecases
disp: msm: sde: reset CTL_UIDLE_ACTIVE register only if uidle is disabled
Change-Id: If480e7f33743eb4788549f853ba05e744ecb38d3
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
This change updates copyright description with correct
license marking as per the guidelines.
Change-Id: Ia74b721e78afcc7f8e88bcbccfcf15430111ec37
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
With full DSC size of 20k, RT performance issues are seen due to the
stress created during larger prefill needed to fill up the 20k DSC buffer.
Limiting DSC size to 10k helps to mitigate these RT performace issues.
This change adds support for this based on new flag has_reduced_ob_max
in sde_mdss_cfg data structure. Flag has_reduced_ob_max has be set
true only on targets where its recommended.
Change-Id: I649d213bcd378025bd0548fb982b55c98c99224f
Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
Dedicated registers are introduced for DSC 4HS merge block
programming from MDSS.9.0. This change adds support in the
driver to identify the change using a DSC feature flag
and separates out 4HS merge block programming to use appropriate
registers based on the DSC HW feature.
Change-Id: Ia64a1ed4bc5f5f301ab422144916cdce2a1dadac
Signed-off-by: Michael Ru <mru@codeaurora.org>
Signed-off-by: Jeykumar Sankaran <quic_jeykumar@quicinc.com>
Current DSC intial line calculation is giving extra line on top of
recommended value from systems since number of active soft slices
considered is wrong. Fix the number or usage of active soft slices
in an encoder to align dsc initial line with recommended setting.
Change-Id: I321260e22b7824b8c481a55b54831ce9535661cc
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
Update dsc configuration and pps programming for 422 and
420 encoding as per the DSC hardware spec.
Change-Id: I4251614cdcd550ed724b1d0dba4846cada4b5392
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
Current code does output buffer max_addr calculation based on dsc id.
Made changes to calculate ob_max_addr based on dsc native422 support.
Change-Id: I01922750f1e9d6cb45615acc1c473891fc648e5d
Signed-off-by: Andhavarapu Karthik <kartkart@codeaurora.org>
Fix dlkm compilation errors that are due to the use of -Werror
flags used by the build system.
Change-Id: I5e1e9bc63c1361d73e4930aab123212717872ecb
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
This change programs both the ich_rst_manual_override and the
ich_rst_manual_value in the DSC encoder to override the hw behavior.
This override is needed to ensure the position of ich_reset is not
changed during the PPS session.
Change-Id: Ia7619a97beeea495706b4327c34fc49ef2298583
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
This change add right only pu support by allowing the dsc to be
flushed when one of the dsc is getting disabled. Since the crtc
swaps the mixers in case of right only partial update, this change
fixes the active display mask passed to encoder so that always the
left only dsc gets programmed. This change also fixes layer mixer
configuration where only one layer mixer is driving the partial
update, the other mixer's configuration is disabled.
Change-Id: I2dd2e9a347797bfe07c90e0ca7f999d151fba933
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Add support for all 4LM topologies in new DCE encoder framework.
This change also aligns with the new way of checking topology
information.
Change-Id: I5358d60634070bdb26059056db884ad4161c073e
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Add support for all 4LM topologies in new DCE encoder framework.
This change also aligns with the new way of checking topology
information.
Change-Id: I20785c96569fd07cbd8016d244a7e4c929bfa071
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
This change fixes issues which causes corruption for dual dsi
dsc panel. It fixes the number of slices configured on
dsc hw block and handles deriving correct picture width from
mode timings. Additionally it fixes the core max buffer sizes
used by the hw block.
Change-Id: Iec0ef80528425ffcb5f29d469bd181eb7040de16
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
This change adds implementation to configure DSC 1.2 block
registers to enable both dsc1.1 and dsc1.2 specifications.
Change-Id: I2307d7dace05bf20384d3221e9aca65e296b12bd
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
